Designing for 448G: Modulation, DSP, and Channel Trade-offs in High-Speed SerDes


Discover practical solutions and engineering insights for deploying 448G SerDes in AI and HPC cluster networks. In this white paper, you’ll learn: The impact of retimed vs. unretimed host architectures on signal integrity and power Key trade-offs between PAM4 and PAM6 modulation Channel design simulations and DSP implications using real-world 448G topologies Equalization stra... » read more

Race to 448 Gbps


The relentless growth in data center and AI workloads is accelerating the need for faster, more efficient interconnect technologies. As applications like large language models and distributed training infrastructures push the limits of bandwidth, 400/800G Ethernet is quickly becoming a bottleneck. To support next-generation performance at 1.6T and 3.2T system levels, engineers must enable relia... » read more