tag: Real Intent

Blog Review: March 5
By Ed Sperling - 05 Mar, 2014 - Comments: 0

ARM’s Lori Kate Smith has discovered an unusual electronic billboard advertisement for shampoo on a train platform in Sweden. Watch what happens when the train goes by. Mentor’s J. VanDomelen puts a magnifying glass on the U.S. Defense budget and where the money is going. Times have changed with technology. Who needs soldiers? Cadence’s Brian Fuller interviews Mindtree CTO S. Janaki... » read more

The Week In Review: Design
By Ed Sperling - 28 Feb, 2014 - Comments: 0

Tools Cadence rolled out a new verification planning and management tool that is based on SQL, which greatly improves functionality and performance and offers multi-user, multi-engine and multi-analysis capabilities. Database technology—in this case, Structured Query Language—remains one of the very few software platforms that can harness multiple processors effectively. Synopsys unveil... » read more

Design And Verification Survey Results
By Graham Bell - 27 Feb, 2014 - Comments: 1

Previously I have blogged about the verification surveys that Real Intent runs at tradeshows throughout the year.  We find it useful to track trends in tool needs and reveal what are the pain points designers are feeling.  I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing re-spins. This year, I would like ... » read more

Is Verification At A Crossroads?
By Ann Mutschler - 27 Feb, 2014 - Comments: 1

As SoC verification methodologies and technologies have continued to mature, it’s an interesting time for engineering teams as they look to meet time to market goals and cut costs in an environment of cutthroat profit margins. Whether it is hardware emulation, FPGA prototyping, virtual prototyping or traditional software simulation, each platform has its strengths and drawbacks, with overl... » read more

Blog Review: Feb. 26
By Ed Sperling - 26 Feb, 2014 - Comments: 0

Got enough time for verification? How about a verification conference? In preparation for DVCon, Real Intent’s Graham Bell grills a panel of experts on where design ends and verification begins. The answer: It depends. Mentor’s Dennis Brophy points to the new version of the Universal Verification Methodology as a reason to attend DVCon next week. Even if you don’t plan to attend, ther... » read more

Hardware-Software Rift Persists
By Brian Bailey - 13 Feb, 2014 - Comments: 0

Last month Semiconductor Engineering published an article about power optimization and the roles of the hardware and software teams in reducing energy consumption. The article portrayed the hardware team adding lots of capabilities for power reduction, while the software team was not making full use of those capabilities. That article made the rounds in a couple of LinkedIn forums populated ... » read more

Blog Review: Feb. 5
By Ed Sperling - 05 Feb, 2014 - Comments: 0

Mentor’s J. VanDomelen notes that the Mars colonization selection process has begun, with the actual colonization scheduled to begin in 2025. Remember to bring your own air, water, food, a sewing kit, and lots of reading material. You also may need leg weights for bone density maintenance. What happens if you build a processor using memory as the starting point? Cadence’s Richard Goerin... » read more

The Growing Verification Challenge
By Ed Sperling - 30 Jan, 2014 - Comments: 1

As complexity continues to mount in designing SoCs, so does the challenge of verifying them within the same time window and using the same compute and engineering resources. Chipmakers aren’t always successful at this. In many cases they have to put more engineers on the verification and debug at the tail end of a design to get it out the door on or close to schedule. In many cases that al... » read more

The Road Ahead For 2014: Tools
By Brian Bailey - 30 Jan, 2014 - Comments: 0

In the third and final part of this predictions series we see the natural conclusion of market shifts that are driving changes in semiconductors, and which in turn drive the tools and IP needed to create those systems. To be expected, the changes fall into a few areas: New tools, techniques and changes required for smaller geometries; A migration to higher-levels of abstraction and the... » read more

Billion-Gate Signoff
By Graham Bell - 30 Jan, 2014 - Comments: 0

At last year’s Design and Verification Conference in San Jose, Real Intent had a tutorial session on “Pre-Simulation Verification for RTL Sign-Off.” This was a start of conversation in the industry that we have seen grow through DAC 2013 in Austin, and which is getting louder each day. Verification companies are now talking about crossing the billion-gate threshold and what can be done to... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy