Industry Scorecard For 2014


At the end of last year, Semiconductor Engineering asked the industry about the developments they expected to see in 2014. If you care to refresh your memory, they were categorized under markets, semiconductors and development tools. Now it is time to look back and see how accurate those predictions were and where they fell short. Markets The obvious trend, at the beginning of the year, wa... » read more

Problems Lurk In SoC Boundaries


Interfaces always have been a problem, because only rarely does anyone have responsibility for them. Responsibilities generally are tied to functional blocks with the prevailing notion that if all blocks do the right thing, they will also behave correctly when brought together. Design teams that believe this eventually find out the fallacy of this assumption. To make matters worse, these are of... » read more

An Architectural Choice Overdue For Change


The past appears to be a lot simpler than the present and when we look into the future, the right decisions often look highly uncertain. This is the value of hindsight, but also includes the notion that the winner gets to write history. What semiconductors look like today could have been very different if different decisions had been made 20 years ago. What if the industry had adopted a paralle... » read more

Are More Processor Cores Better?


Up until the early 2000s, each generation of processor was faster, used more exotic architectures, had deeper pipelines, used more transistors, ran at higher clock frequencies and consumed more power. In fact power was rising faster than performance and led to the extrapolation that within a few generations, processors would run as hot as nuclear reactors. Something had to change, and that c... » read more

Keeping Up With The Productivity Challenge


Until recently, EDA software rode the coattails of increasing processor performance as part of its drive to continue providing faster and more powerful development software to the people designing, among other things, the next generation of faster processors. It was a fortuitous ring. Around the turn of the century, with the migration to multi-core computing systems, all of that changed. In ord... » read more

Where Do We Stand With CDC


Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of [getentity id="22674" e_name="Arteris"]; Shaker Sarwary, VP of Formal Verification Products at [getentity id="22026" e_name="Atrenta"]; Pranav Ashar, CTO at [getentity id="22416" e_name="Real Intent"]; and Namit Gupta, CAE, Verification Group at [getentity id="22035" e_nam... » read more

How To Cut Verification Costs For IoT


Cost is one of the main factors limiting proliferation of the [getkc id="76" comment="Internet of Things"] (IoT), and when looking at the design and [getkc id="10" kc_name="Verification"] methodologies in place today, verification is a prime candidate for closer inspection. For today’s complex [getkc id="81" kc_name="SoCs"], the cost of verification has been rising faster than design and it h... » read more

Fixing Functional Coverage


Constrained random test pattern generation entered the scene a couple of decades ago as a better way to spend time and resources for the creation of stimulus. Stimulus definition had become an arduous task—defining the patterns necessary to exercise designs of increasing size. It was successfully argued that spending time writing models instead of creating stimulus and having a computer p... » read more

Where Do We Stand With CDC?


Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of Arteris; Shaker Sarwary, VP of Formal Verification Products at Atrenta; Pranav Ashar, CTO at Real Intent; and Namit Gupta, CAE, Verification Group at Synopsys. What follows are excerpts of that conversation. SE: What are the biggest use models for CDC verification today... » read more

Where Do We Stand With CDC?


Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of Arteris; Shaker Sarwary, VP of Formal Verification Products at Atrenta; Pranav Ashar, CTO at Real Intent; and Namit Gupta, CAE, Verification Group at Synopsys. What follows are excerpts of that conversation. SE: While not a new aspect of design, clock domain crossing is... » read more

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