tag: Reliance Memory

Week In Review: Design, Low Power

By Jesse Allen - 15 May, 2020 - Comments: 0

Tools & IP Synopsys released a range of IP for TSMC's 5nm process technology. It includes interface PHY IP such as 112G/56G Ethernet, Die-to-Die, PCIe 5.0, CXL, and CCIX; memory interface IP for DDR5, LPDDR5, and HBM2/2E; die-to-die PHYs for 112G USR/XSR connectivity and High-Bandwidth Interconnect; and foundation IP including logic libraries, multi-port memory compilers, and TCAMs. Sma... » read more

Trending Articles

Intel Vs. Samsung Vs. TSMC

Foundry competition heats up in three dimensions and with novel technologies as planar scaling benefits diminish.

Chip Industry Week In Review

Softbank's acquisition; advanced packaging funding; glass substrates; engineered copper wire; semi equipment set new record; HBM4; AI chips rake in funding; X-ray inspection; apprenticeships.

by The SE Staff

Chip Industry Week In Review

DAC; CHIPS funding; CXL standards; Nexperia investment; US curbs tech investments; Accellera's Federated Simulation Group; European sustainability concerns; SIA's tracking tool; Multibeam's multicolumn litho system.

by The SE Staff

Chip Industry Week In Review

Leading-edge foundry plans; DoD IC center; 300mm funding; Intel's apprenticeship program; metrology and test acquisitions; Keysight's chiplet PHY simulation; thermal management in 3D-ICs; foundry growth.

by The SE Staff

Startup Funding: Q2 2024

Big rounds for AI chips; 91 startups raise $2.6 billion.

Knowledge Centers
Entities, people and technologies explored

Related Articles

Intel Vs. Samsung Vs. TSMC

Foundry competition heats up in three dimensions and with novel technologies as planar scaling benefits diminish.

by Ed Sperling

Electromigration Concerns Grow In Advanced Packages

Higher density, heat, and more materials make it harder to ensure reliability.

by Laura Peters

The Race To Glass Substrates

Replacing silicon and organic substrates requires huge shifts in manufacturing, creating challenges that will take years to iron out.

by Gregory Haley

What Works Best For Chiplets

Not all chiplets are interchangeable, and options will be limited.

by Anne Meixner

Controlling Warpage In Advanced Packages

Mechanical stresses increase with larger sizes and heterogeneous materials.

by Laura Peters

Electrically Controlled All-AFM Tunnel Junctions on Silicon with Large Room-Temperature Magnetoresistance (Northwestern)

by Technical Paper Link

Architecting Chips For High-Performance Computing

Data center IC designs are evolving, based on workloads, but making the tradeoffs for those workloads is not always straightforward.

by Ann Mutschler

EDA Looks Beyond Chips

System design, large-scale simulations, and AI/ML could open multi-trillion-dollar markets for tools, methodologies, and services.

by Ed Sperling

About

Navigation

Connect With Us

Facebook
Twitter @semiEngineering
LinkedIn
YouTube

Copyright ©2013-2024 SMG | Terms of Service | Privacy Policy