Accelerating Toshiba’s Advanced System-on-Chip (SoC) Design with Synopsys’ Fusion Compiler

By Synopsys - 23 Oct, 2019 - Comments: 0

Authors: Mitchy M. Mitsuyasu, Senior Specialist, Semiconductor R&D, Toshiba Electronic Device & Storage Corp.; Akira Nikaido, Director Product Marketing, Synopsys. Toshiba Electronic Devices & Storage Corporation, part of the broader Toshiba, Kawasaki Japan, has long been a technology leader in Advanced SoCs spanning multiple, key market verticals. This includes automotive, communications, I... » read more

Opposites Attract: IP Standardization vs. Customization

By eSilicon - 25 Sep, 2019 - Comments: 0

Have you had a look lately at an autonomous driving SoC? Have you noticed, besides the cool machine learning stuff, the grocery list of third-party IP that goes into it? It is a long, long list, composed of pieces both big and small and quite diverse. For example, interface and peripheral PHYs and controllers, memories, on-chip interconnects, PVT monitors and PLLs. In some highly-publicized exa... » read more

Challenges To Building Level 5 Automotive Chips

By Ann Mutschler - 05 Sep, 2019 - Comments: 0

It’s an exciting time in the automotive space, and this is especially true when it comes to all of the activity around autonomous driving and the path to achieving full Level 5 autonomy. The technology is complex, the ecosystem seems to get more complex by the day, and simulating autonomous systems safely makes this an extremely fascinating area from an engineering perspective. At the heart o... » read more

A Complete System-Level Security Verification Methodology

By Cadence - 04 Sep, 2019 - Comments: 0

Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

The Power Of Virtual Prototyping

By Arm - 12 Jun, 2019 - Comments: 0

As embedded SoCs continue to become more powerful and complex, beating the market may very well rely on non-traditional approaches to product design and development. Software-based methodologies involving virtual prototypes are helping to prove out designs earlier and enable companies to parallelize hardware and software development. Click here to download PDF. » read more

SOC Design & IP Management—A Must For Functional Verification

By Cliosoft - 05 Jun, 2019 - Comments: 0

As a part of the verification flow, verification teams perform different types of simulations based on the nature of the design. The simulations include digital logic functional simulations, mixed-signal functional simulations, power-aware simulations, formal verification runs and gate-level simulations. For a signoff, all planned tests must pass in all four types of simulations. In addition t... » read more

Accelerating Toshiba’s SoC Design with Fusion Compiler

By Synopsys - 13 Mar, 2019 - Comments: 0

This white paper discusses how Toshiba and Synopsys worked closely to bring-up Fusion Compiler and deploy it throughout Toshiba's advanced proprietary Tachyon Design System. With improved power, performance, and area (PPA), faster time-to-results and a predictable design flow have been validated on the latest, differentiated automotive SoC ASIC products, and Fusion Compiler is being broadly dep... » read more

Quantifying the Value of On-Chip Debug

By UltraSoC - 19 Dec, 2018 - Comments: 0

White paper authored by Semico Research, quantifies the benefits of using on-chip debug and monitoring technology, specifically UltraSoc's technology. Rising design complexityIn the last several years, contemporary SoCs (system-on-a-chip) have become increasingly complex. They now consist of 100s of millions of gates, 100 or more discrete semiconductor intellectual property (SIP) blocks, hi... » read more

Accelerate SoC Simulation Time of Newer Generation FPGAs

By Aldec - 26 Sep, 2018 - Comments: 0

Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. Read more. » read more

ISO26262: The Case for Embedded Analytics in Automotive (updated: V.4.0)

By UltraSoC - 26 Sep, 2018 - Comments: 0

From advanced driver assistance systems (ADAS) to a new generation of robots and medical systems, we are seeing an explosion in the development of cyber-physical systems. Because these systems use advanced software to interact with the physical world, safety is a paramount issue but one that is reflected in many industries by the use of safety standards based on a philosophy of risk assessme... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: SoC design