tag: SoCs

Pain Management
By Ed Sperling - 10 Apr, 2014 - Comments: 0

In part one of this series, the focus was on overlapping and new pain points in the semiconductor flow, from initial conception of what needs to be in a chip all the way through to manufacturing. Part two looks at how companies are attempting to manage that pain. It’s no secret that [getkc id="81" kc_name="SoC"]s are getting more complicated to design, debug and build, but the complexity i... » read more

Tech Talk: Debugging IP
By Ed Sperling - 03 Apr, 2014 - Comments: 0

Just because IP is standard doesn't mean it will function as expected in a complex SoC. Ravindra Aneja, senior technical marketing manager at Atrenta, looks at what needs to be done to make sure everything works together. [youtube vid=wlDabbrF2zU] » read more

SoC Integration Mistakes
By Ed Sperling - 13 Feb, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion. SE... » read more

How To Speed Up Verification
By Ann Mutschler - 30 Jan, 2014 - Comments: 0

Software requirements have changed the tapeout process in today’s SoCs so much that it isn’t uncommon to hear a design can’t be released because Android hasn’t booted. “It’s one of those things where you really understand that what used to be classic hardware verification that said ‘the chip is done’ is heavily impacted by if it actually does software things,” noted Frank S... » read more

It’s Time To Talk…
By Ed Sperling - 05 Dec, 2013 - Comments: 0

It’s bad enough that hardware engineers can’t explain what they do to other people outside of their world, but increasingly they can’t explain it outside of their narrow slice of an SoC. Engineers routinely introduce themselves as scientists, teachers, handymen, consultants, and occasionally even as arms dealers. The problem is that the tasks they handle are so complex and intertwined ... » read more

Experts At The Table: Debug
By Ed Sperling - 31 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: There are separate areas being created in devices, s... » read more

Trending Back To ASICs
By Ann Mutschler - 24 Oct, 2013 - Comments: 0

True to its cyclical nature, the semiconductor industry is swinging back toward ASICs from more diversified approaches such as FPGAs. This dynamic is evident at companies such as Apple. “At one point we thought Apple was being a contrarian,” said Drew Wingard, CTO at Sonics. “Everybody else on the systems side was shedding their silicon people. The easiest counterpoint to what Apple wa... » read more

Experts At The Table: Debug
By Ed Sperling - 18 Oct, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: The amount of IP is increasing and i... » read more

Critical Choices
By Ed Sperling - 10 Oct, 2013 - Comments: 0

There’s been a lot of talk about what’s good enough. Is 10 hours of battery life enough? If the tradeoff is between a smaller battery and extra hour of battery life, which is more important? Those kinds of discussions are at the heart of consumer electronics. Ultra-thin smart phones are more attractive than fat ones, and they’re easier to put in your pocket. But a new kind of discussio... » read more

Divide, Abstract And Conquer
By Ed Sperling - 03 May, 2013 - Comments: 0

For years, the motto among design and verification engineers has been to look at the individual pieces of a design because it’s impossible to have a single tool or even an integrated collection of tools that can debug everything. That approach isn’t changing, but the method for getting there is. The driver behind this shift is a familiar one—growing complexity. Even platforms and subsy... » read more

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