tag: Sonatus

Chip Industry Week in Review

By The SE Staff - 15 May, 2026 - Comments: 0

Global The U.S. created a licensing path for Nvidia H200 shipments in January and has since approved sales to 10 Chinese companies, but so far no shipments have been confirmed, reports Reuters. With a looming end-of-year expiration, SIA, SEMI, and other business groups are urging Congress to extend the US semiconductor tax credit and expand it to cover semiconductor design and other act... » read more

Shifting Toward Software-Defined Vehicles

By John Koon - 05 Jan, 2023 - Comments: 0

Apple reportedly is developing a software-defined vehicle. But so are Renault, Hyundai, General Motors, and just about everyone else. Some of the benefits of SDVs include increased comfort, convenience, safety, reliability, and remote software and firmware updates. Preventive and predictive maintenance, and remote diagnostics, can be done more conveniently over the air, while vehicle behavio... » read more

Trending Articles

The Sub-2nm Paradox

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

Chip Industry Week In Review

AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; memory test facility; Taiwan investments; SiC teamup; DRAM sizing; sequentially stacking silicon; MIPI A-PHY SerDes automotive compliance.

by The SE Staff

Chip Industry Week In Review

Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon's 1.5 micron L/S litho; IC market rises; Apple's chiplet era; 4,500 chips per AI server rack; HBM price hikes; quantum IPO, chip and roadmap; SiC guidelines; MXenes; EV outlook; autonomous edge chiplets.

by The SE Staff

Toward Agentic Verification

Using AI agents for verifying designs holds huge potential, but can it deliver? And what comes next?

by Brian Bailey

Swapping Out Chiplets: I/Os Vs. Compute

Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?

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Advanced Packaging Limits Come Into Focus

Mechanical and process control limits are now shaping what can be manufactured at scale.

by Gregory Haley

Startup Funding: Q1 2026

Massive rounds for AI, EDA, and manufacturing; 80 startups raise $8.4B.

by Jesse Allen

All AI Data Center Interconnects Will Be Optical Within 5 Years

InP and SiPho join CMOS as critical technologies. Lasers, CPO and OCS will be everywhere (indium phosphide, silicon photonics, co-packaged optics, optical circuit switch).

by Geoff Tate

Making Hybrid Bonding Better

Why this technology is so essential for multi-die assemblies, and how it can be improved.

by Laura Peters

When Semiconductor Materials Misbehave

The gap between lab performance and fab reality is growing wider as packages grow more complex.

by Gregory Haley

The Sub-2nm Paradox

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

by Ed Sperling

TSMC Tech Symposium 2026, By The Numbers

Foundry rolls out aggressive new roadmap, focusing on area, power, and latency.

by Barry Pangrle

CPO Is Extending The Limits Of What’s Possible In AI Data Centers

Co-packaged optics technology will have a big impact on system power and the cost of data movement.

by Ann Mutschler

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