LLM-driven, Formal Verification-Assisted Framework For Functional-Safety-Oriented Fault Criticality Assessment (ASU, TI)


Researchers from Arizona State University and Texas Instruments India published a technical paper titled “SafeGen: LLM-Driven Assertion Generation and Fault Criticality Evaluation for Functional Safety.” Abstract Excerpt: “This paper presents SafeGen, an LLM-driven, formal-verification-assisted framework for functional-safety-oriented fault criticality assessment.” The paper also ... » read more

The Race To Zero Defects


By Jeff Dorsch and Ed Sperling Testing chips is becoming more difficult, more time-consuming, and much more critical—particularly as these chips end up in cars, industrial automation, and a variety of edge devices. Now the question is how to provide enough test coverage to ensure that chips will work as expected without slowing down the manufacturing process or driving up costs. Balanci... » read more