Beyond BPD: Backside Clock and Signal Routing for Sub-3nm (UT Austin, Intel)


A new technical paper titled "Beyond Backside Power: Backside Signal Routing as Technology Booster for Standard Cell Scaling" was published by researchers from University of Texas at Austin and Intel. Abstract "Advances in process technology enabling backside metals and contacts offer new Design-Technology Co-Optimization (DTCO) opportunities to further enhance power, performance, and area ... » read more

Artificial Neural Network (ANN)-Based Model To Evaluate The Characteristics of A Nanosheet FET (NSFET)


This new technical paper titled "Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors" was published by researchers at SungKyunKwan University, Korea. Abstract: "In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generat... » read more