Accelerate SSD Software Development And System Validation


The amount of data coming at us or that we produce ourselves in our daily lives continues to grow exponentially. It’s become the norm to stream movies and TV series from Netflix, as well as upload our own videos on YouTube. On top of this, a major shift in automotive (ADAS, autonomous driving) and surveillance are boosting the amount of data exchange that is happening every second. With th... » read more

The Problem With Post-Silicon Debug


Semiconductor engineers traditionally have focused on trying to create 'perfect' GDSII at tape-out, but factors such as hardware-software interactions, increasingly heterogeneous designs, and the introduction of AI are forcing companies to rethink that approach. In the past, chipmakers typically banked on longer product cycles and multiple iterations of silicon to identify problems. This no ... » read more

Can Debug Be Tamed?


Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

Reverse Debug


Chun Chan, product applications engineering director at Synopsys, talks with Semiconductor Engineering about testbench debug and how adding time markers can speed time to signoff. https://youtu.be/tx_89M1bq3Q » read more

Efficient Low-Cost Implementation of NB-IoT for Smart Applications


NB-IoT is an emerging technology for narrowband wireless communication standardized by 3GPP. It has been designed with a focus on minimizing end-user equipment processing requirements and power consumption to enable the massive deployment of low-cost devices for a broad range of smart applications. This white paper highlights the key challenges of NB-IoT modem design. It proposes a hardware/sof... » read more

Blog Review: Feb. 27


Mentor's Harry Foster checks out the trends in language and library adoption for IC/ASIC designs and finds increased adoption of SystemVerilog for both design and verification while UVM remains the dominant verification methodology. Synopsys' Taylor Armerding chats with Chris Clark of Synopsys and Tim Weisenberger of SAE about the weakest points in automotive security and why it's time to mo... » read more

Week In Review: Design, Low Power


Tools OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effe... » read more

Week in Review: IoT, Security, Auto


Internet of Things Cattle ranchers in Australia are using solar-powered ear tags to keep track of their herds, connecting through LoRa technology to locate their bulls, cows, heifers, and steers. SODAQ of the Netherlands and Lacuna Space of the U.K. are providing the Internet of Things technology and satellite-based LoRa connectivity to make this possible. “The main differentiator for LoRa o... » read more

Using AI Data For Security


Artificial intelligence is migrating from the cloud to IoT edge devices. Now the question is how to apply that same technology to protect data and identify abnormal activity in those devices and the systems connected to them. This is a complex problem because AI is being used on multiple fronts in this battle, as well as for multiple purposes. The technology has advanced to the point where e... » read more

Blog Review: Feb. 20


Synopsys' Chirag Tyagi examines how Display Stream Compression 1.2 allows the commonly used MIPI DSI display interface to support 8k UHD displays in applications like infotainment and AR/VR even with the limited bandwidth of PHY layers. Cadence's Paul McLellan listens in on a panel discussion at DesignCon on how to create PDKs for silicon photonics so non-photonics experts can complete at le... » read more

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