tag: Synopsys

Revolutionizing Semiconductor Development With GPU-Enhanced Atomistic Modeling
By Anders Blom - 22 May, 2025 - Comments: 1

There are many challenges in the development of a modern semiconductor chip, from front-end architecture simulation to final signoff. Volume manufacturing has its own set of challenges, while silicon lifecycle management (SLM) extends into field deployment and aging concerns. Underlying this entire development flow, however, lie the materials used to build the actual chips. Guiding the explorat... » read more

Cooling Chips Still A Top Challenge
By Bryon Moyer - 22 May, 2025 - Comments: 0

Increasing levels of semiconductor integration means more work needs to be done in smaller spaces, which in turn generates more heat that needs to be dissipated. Managing heat dissipation in advanced node dies and in multi-die assemblies is critical to their functionality and their longevity. And while much of the focus has been on improving power efficiency, which reduces the rate of power ... » read more

Future-proofing AI Models
By Ann Mutschler - 21 May, 2025 - Comments: 0

Experts At The Table: Making sure AI accelerators can be updated for future requirements is becoming essential due to the rapid introduction of new models. Semiconductor Engineering sat down to discuss the challenges of future-proofing these designs with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vic... » read more

Blog Review: May 21
By Jesse Allen - 21 May, 2025 - Comments: 0

Synopsys’ Frank Malloy listens in on a panel discussing the engineering challenges introduced by multi-die designs, from multi-physics interactions that impact power and thermal integrity to the availability of multi-die packages and industry standards. Siemens’ Bruce Caryl shows how to determine how much a design’s power delivery network is contributing to jitter on the output drivers... » read more

More Data, More Redundant Interconnects
By Ed Sperling - 19 May, 2025 - Comments: 0

The proliferation of AI dramatically increases the amount of data that needs to be processed, stored, and moved, accelerating the aging of signal paths through which that data travels and forcing chipmakers to build more redundancy into the interconnects. In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipma... » read more

Die-to-die Interconnect Standards In Flux
By Bryon Moyer - 15 May, 2025 - Comments: 0

UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release. But the fact that many of the new features are optional seems to have been lost in much of the public discussion. In fact, new capabilities that support a possible future chiplet marketplace are not required for designs that don’t target that marketplace. ... » read more

High-Speed Test IO: Addressing High-Performance Data Transmission And Testing Needs For HPC & AI
By Lakshmi Jain - 15 May, 2025 - Comments: 0

By Lakshmi Jain and Wei-Yu Ma The AI and HPC industries are rapidly shifting toward chiplet-based designs to achieve unprecedented levels of performance, as traditional monolithic system-on-chip (SoC) architectures face scaling limitations. This transition is fueled by the rise of heterogeneous integration, which is driving innovation across the semiconductor sector. However, this advancemen... » read more

Development Flows For Chiplets
By Brian Bailey - 15 May, 2025 - Comments: 2

Chiplets offer a huge leap in semiconductor functionality and productivity, just like soft IP did 40 years ago, but a lot has to come together before that becomes reality. It takes an ecosystem, which is currently very rudimentary. Today, many companies have hit the reticle limit and are forced to move to multi-die solutions, but that does not create a plug-and-play chiplet market. These ear... » read more

AI Accelerators Moving Out From Data Centers
By Ann Mutschler - 15 May, 2025 - Comments: 0

Experts At The Table: The explosion in AI data is driving chipmakers to look beyond a single planar SoC. Semiconductor Engineering sat down to discuss the need for more computing and the expanding role of chiplets with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vice president of marketing at Expedera; ... » read more

Blog Review: May 14
By Jesse Allen - 14 May, 2025 - Comments: 0

Siemens’ Stephen V. Chavez finds that proper PCB high voltage spacing between conductive elements is key to reliability and understanding the principles of clearance (through-air spacing) and creepage (along-surface spacing) is critical. Cadence’s Frank Ferro checks out how the new HBM4 standard boosts bandwidth and addresses key issues in the data center, including the growing size of L... » read more

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