Week in Review – IoT, Security, Autos

By Jeff Dorsch - 04 Oct, 2019 - Comments: 0

Products/Services Cadence Design Systems is working with Adesto Technologies to grow the Expanded Serial Peripheral Interface (xSPI) communication protocol ecosystem, for use in Internet of Things devices. The Cadence Memory Model for xSPI allows customers to ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP octal xSPI ... » read more

Week in Review – IoT, Security, Autos

By Jeff Dorsch - 06 Sep, 2019 - Comments: 0

Products/Services Rambus entered an exclusive agreement to acquire the Silicon IP, Secure Protocols, and Provisioning business from Verimatrix, formerly known as Inside Secure. Financial terms were not revealed. The transaction is expected to close this year. Rambus will use the Verimatrix offerings in such demanding applications as artificial intelligence, automotive, the Internet of Things, ... » read more

The Week In Review: IoT

By Jeff Dorsch - 01 Sep, 2017 - Comments: 0

Finance Dublin-based Cubic Telecom has taken in €40 million (about $47.6 million) in Series C funding, bringing its total funding to €75 million (around $89.25 million). Audi Electronics Venture and Qualcomm are existing investors participating in the new round of funding, joined by new investors Ireland Strategic Investment Fund and Valid Soluciones Tecnologicas SAU. Cubic will use the mo... » read more

The Week In Review: IoT

By Jeff Dorsch - 05 May, 2017 - Comments: 0

Q&A Francine Berman, a computer science professor at Rensselaer Polytechnic Institute, talks about ethical issues in the Internet of Things in this interview. She says, “First of all, we’re just at the tip of the iceberg in what is arguably going to be a brave new world. And it’s highly heterogeneous: We’ll be seeing a lot more autonomous systems, we’ll be seeing enhanced humans and ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

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Week in Review – IoT, Security, Autos

Week in Review – IoT, Security, Autos

The Week In Review: IoT

The Week In Review: IoT