tag: University at Albany

Chip Industry Week in Review

By The SE Staff - 05 Sep, 2025 - Comments: 0

Cadence plans to buy Hexagon AB's design and engineering business to accelerate expansion in physical AI and system design and analysis. Cadence will pay ~US$3.1 billion in cash and issue stock, with the deal expected to close in early 2026. PWC issued a 104-page in-depth analysis of semiconductor technology and markets, highlighting a broad swath of changes: $1T in annual revenue by 2030, ... » read more

Research Bits: Sept. 24

By Jesse Allen - 24 Sep, 2024 - Comments: 0

Modeling negative capacitance Researchers from Lawrence Berkeley National Laboratory developed an open-source 3D simulation framework capable of modeling the atomistic origins of negative capacitance in ferroelectric thin films at the device level. When a material has negative capacitance, it can store a greater amount of electrical charge at lower voltages. The team believes the FerroX fra... » read more

Trending Articles

The Sub-2nm Paradox

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

Chip Industry Week In Review

Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon's 1.5 micron L/S litho; IC market rises; Apple's chiplet era; 4,500 chips per AI server rack; HBM price hikes; quantum IPO, chip and roadmap; SiC guidelines; MXenes; EV outlook; autonomous edge chiplets.

by The SE Staff

Chip Industry Week In Review

Onsemi to buy Synaptics; IBM's 7Å chip w/40% more SRAM area; 1nm MoS2 nanotubes; AI pressure points; memory updates; $250M CHIPS Act award; trade secret theft; new advanced packaging site; MEMS capacity; humanoids; earnings.

by The SE Staff

Chip Industry Week In Review

Apple-Intel is on, says Trump; Amkor's big win; Intel 18A-P; Amazon to sell its AI chips; Rambus' automotive RoT; Brewer's buy; VLSI Symposium tech; CHIPS Act funding; MIT sensor; RISC-V CPU fuzzing.

by The SE Staff

Agentic AI Is Changing Data Center Architectures

Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs, GPUs, and NPUs to eliminate memory bottlenecks, reduce latency, and boost efficiency.

by Ann Mutschler

Knowledge Centers
Entities, people and technologies explored

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Advanced Packaging Limits Come Into Focus

Mechanical and process control limits are now shaping what can be manufactured at scale.

by Gregory Haley

Startup Funding: Q1 2026

Massive rounds for AI, EDA, and manufacturing; 80 startups raise $8.4B.

by Jesse Allen

All AI Data Center Interconnects Will Be Optical Within 5 Years

InP and SiPho join CMOS as critical technologies. Lasers, CPO and OCS will be everywhere (indium phosphide, silicon photonics, co-packaged optics, optical circuit switch).

by Geoff Tate

When Semiconductor Materials Misbehave

The gap between lab performance and fab reality is growing wider as packages grow more complex.

by Gregory Haley

The Sub-2nm Paradox

Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

by Ed Sperling

TSMC Tech Symposium 2026, By The Numbers

Foundry rolls out aggressive new roadmap, focusing on area, power, and latency.

by Barry Pangrle

CPO Is Extending The Limits Of What’s Possible In AI Data Centers

Co-packaged optics technology will have a big impact on system power and the cost of data movement.

by Ann Mutschler

Memory Wall Gets Higher

With SRAM failing to scale in recent process nodes, the industry must assess its impact on all forms of computing. There are no easy solutions on the horizon.

by Brian Bailey

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