Impact of Band-to-Band Tunneling in the CTL of V-NAND Flash Memory (U. of Seoul, Samsung)


A new technical paper, "Impact of Band-to-Band Tunneling in the Charge Trap Layer of NAND Flash Memory," was published by researchers from University of Seoul and Samsung Electronics. Abstract "This article investigates the impact of band-to-band tunneling (BTBT) occurring in the charge trap layer (CTL) of vertical NAND (V−NAND) flash memory under excessive erasure conditions and aggres... » read more

FeFETs With Laminated Gate Stacks For Radiation Resilience in Vertical NAND (Georgia Tech)


A new technical paper, "Enabling Radiation Hardness in Solid-State NAND Storage Utilizing a Laminated Ferroelectric Stack," was published by researchers at Georgia Tech. Abstract "NAND flash forms the core of modern solid-state storage, which is critical for data-intensive AI applications, yet charge-trap NAND suffers rapid threshold-voltage (Vth) degradation under ionizing radiation, causi... » read more

V-NAND PUFs (Seoul National University, SK hynix)


A new technical paper titled "Concealable physical unclonable functions using vertical NAND flash memory" was published by researchers at Seoul National University and SK hynix. The paper proposes "a concealable PUF using V-NAND flash memory by generating PUF data through weak Gate-Induced-Drain-Leakage (GIDL) erase." Find the technical paper here. June 2025. Park, SH., Koo, RH., Yang,... » read more

Monitor Etch Defects on Dies in the Outer Regions Of The Wafer Using ISR


A technical paper titled "Detection of defective chips from nanostructures with a high-aspect ratio using hyperspectral imaging and deep learning" was published by researchers at Samsung Electronics. Abstract: "We have developed an imaging spectroscopic reflectometry (ISR) method based on hyperspectral imaging and deep learning to detect defects in the bottom region of high-aspect-ratio nan... » read more