The Good And Bad Of 2D Materials

Despite years of warnings about reaching the limits of silicon, particularly at leading-edge process nodes where electron mobility is limited, there still is no obvious replacement.

Silicon’s decades-long dominance of the integrated circuit industry is only partly due to the material’s electronic properties. Germanium, gallium arsenide, and many other semiconductors offer superior mobility, but none has yet matched the ease of integration of the Si/SiO₂ system. Even now, when HfO₂-based gate stacks are ubiquitous, silicon’s passivating surface oxide is a critical enabler of the manufacturing process.

The fate of silicon’s previous challengers offers a cautionary tale for proponents of two-dimensional semiconductor materials. A successful process integration scheme includes not just the channel material, but also doping, contacts, and device structures suitable for large-scale designs. While much of the research so far emphasizes the use of 2D materials as computational elements, such as transistors and memristors, they also may be useful in applications such as RF switches and non-metallic electrodes.

Transistor and contact structures
While graphene was the first 2D semiconductor discovered, much of the current research focuses on transition metal dichalcogenides (TMDs) such as tungsten selenide (WSe₂) and molybdenum disulfide (MoS₂). The bandgap and mobility of these materials varies with the number of stacked layers and the amount of strain. On one hand, being able to tune the channel properties simplifies many circuit design problems. On the other hand, uncontrolled variation can have catastrophic yield consequences.

Chin-Sheng Pang, a researcher at Purdue University, and his colleagues suggested that WSe₂, which is air-stable and has a large thickness-dependent bandgap, might be especially relevant for wearable sensors and other flexible devices. Organic thin films, polycrystalline silicon, and most other flexible semiconductors have relatively poor carrier mobility, leading to low packing densities and excessive power consumption. TMDs potentially can overcome these limitations.

In previous work with WSe₂, contact metals have pinned the Fermi level near mid-gap, resulting in ambipolar devices. At the recent IEEE Electron Device Meeting, the Purdue group demonstrated complementary WSe₂ transistors with hafnium dioxide (HfO₂) gate dielectrics, using oxygen plasma doping for PFETs. In their NFETs, a tri-gate electrostatic doping structure allowed independent biasing of the two side gates to produce an n-insulator-n doping profile. The NFET devices achieved a near ideal subthreshold swing on 69 mV/decade, while the PFET value was 90 mV/decade. Whether these devices are applicable to commercial circuits is not clear, though, as they were based on exfoliated WSe₂ flakes. Moreover, the tri-gate structure significantly complicates circuit wiring.

While evaporative metal contacts are easy to make and generally give good results in laboratory devices, a silicon-based contact process is more desirable for large-scale integration. Silicon contacts are well understood in the industry and are easy to dope for work-function tuning, but there have been very few studies of silicon-based contacts for 2D semiconductors. A group at Shandong University in China used a series of simulation studies to investigate silicon contacts for TMDs. They found that (110)-oriented silicon gave low Schottky barrier heights in most cases, with successful passivation with hydrogen and fluorine for n- and p-type contacts, respectively. In p-type contacts, a boron nitride interfacial layer gave a vanishingly small barrier height.

2D semiconductors for in-memory computing
The range of proposed future computing architectures extends well beyond conventional CMOS logic. In fact, in-memory computing is a particularly attractive target for 2D semiconductors because it will require extremely high-density integration. An RRAM array might be constructed with several layers stacked on top of each other, for example, with the data inputs at the top and the results read at the bottom. To minimize sneak path leakage between nodes of the array, each memory element might have a selector transistor stacked vertically above or below it. Ching-Hua Wang and colleagues at Stanford University realized an architecture like this by stacking MoS₂ transistor selectors with a hexagonal boron nitride RRAM array. With a fabrication temperature below 150 ℃, they anticipate relatively simple scaling to arbitrarily many layers, limited primarily by yield.

Another group, also at Purdue, demonstrated phase-change memory devices based on 2D MoTe₂. While most phase change memories depend on a transition between an amorphous and a crystalline phase, MoTe2 transitions between two crystalline phases, 2H and 2H_d. Because the states are structurally close, the kinetics of the transition should be faster than either the ion migration of filament-based RRAMs or the amorphous-to-crystalline transition of other PCRAMs. Initial measurements found switching speeds below 5 nanoseconds, with multiple stable resistance states.

Above and beyond their ability to deliver high density versions of current devices, 2D semiconductors can potentially introduce new device types that depend on their unusual physics. Ruijing Ge and colleagues at the University of Texas at Austin demonstrated “atomristor” non-volatile resistive switching behavior in MoS₂ layers with gold contacts. The switching voltage appears to drive gold substitution into sulfur vacancies. As the number of states occupied by gold ions increases, the monolayer becomes conductive. The device is only a single atomic layer thick, and does not include “filament” forms. Rather, conductive bridge-like switching occurs once enough conductive states exist.

Building the process ecosystem
Most reported work on TMDs uses either exfoliated monocrystalline flakes or MOCVD-grown multicrystalline films. In multicrystalline films, though, grain size variations, the migration of sulfur and other defects can cause inconsistent switching behavior. Most device designers would prefer to use monocrystalline materials. Researchers at Imec, discussing their roadmap for 2D device integration, explained that there are two routes to wafer-scale growth of TMD materials. Growth directly on amorphous dielectrics can give excellent carrier mobility, but the high temperatures and harsh growth chemistries required tend to degrade the dielectric layer.

Alternatively, templated growth followed by layer transfer allows separate optimization of the semiconductor and dielectric deposition processes. Successful transfer depends on clean interfaces and uniform strain, as both strain variability and interface contamination can affect device performance. Inconsistent mechanical forces can cause cracks and wrinkling, while chemical residues can cause doping effects.

Overall, it is clear that much work remains before 2D semiconductors can complement, much less displace, silicon logic technology. But the challenges appear to lie in the realm of engineering and processing issues. The fundamental materials physics does not appear to stand in the way.

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