Week In Review: Design, Low Power

M&A
Siemens acquired Austemper Design Systems, which provides tools for functional safety and safety-critical designs. Founded in 2015, Texas-based Austemper adds state-of-the-art safety analysis, auto-correction and fault simulation technology to address random hardware faults, as well as correct and harden vulnerable areas, subsequently performing fault simulation to ensure the design is hardened and no longer susceptible to errors. Siemens will integrate Austemper’s technology into Mentor’s IC verification portfolio.

Metrics Technologies plans to merge with Montana Systems, an R&D-stage startup building hardware simulation acceleration tools. Metrics provides cloud-based simulation and verification management tools.

MagnaChip, a provider of analog and mixed-signal platforms, sold more than 85 patents and applications covering semiconductor process technologies to Wi-LAN subsidiary Atria Technologies.

Tools
Cadence is moving into the cloud. The company has been architecting many of its products to be massively parallel for improved scalability in cloud environments. The initial portfolio includes tools for circuit simulation, power and EM analysis, logic simulation, formal verification, physical verification, timing signoff, extraction, power integrity and library characterization. Tools are available either in a self-hosted environment or through Amazon Web Services, Microsoft Azure, or Google Gloud. In addition, they announced the Cadence Palladium Cloud, which enables their customers to purchase gate capacity to be used when needed.

Metrics Technologies uncorked a Google Cloud-based SaaS program for on-demand simulation, big data management, and integrated global verification workflows. The solution aims to provide faster regression runtimes with unlimited, on-demand, cloud-based simulation capacity using a pay-by-the-minute model. It offers simulation data analysis through a web-based verification manager with coverage reporting and regression debug tools.

Accellera released the 1.0 version of the Portable Test and Stimulus standard (PSS). PSS defines a specification for stimulus and test scenarios that facilitates the generation of diverse implementations of a scenario that run on a variety of execution platforms, including, simulation, emulation, FPGA prototyping, and post-silicon. With this standard, users can specify a set of behaviors once and observe consistent behavior across multiple implementations.

Mentor, a pioneer of portable stimulus technology since 2004, will fully support the new Accellera Portable Test and Stimulus Standard 1.0 in the upcoming release of its Questa inFact tool. Their customers use the inFact tool to generate UVM SystemVerilog test scenarios to achieve functional coverage at the IP block level with the Questa simulator, and then re-use the test scenarios to generate C/C++ tests for traffic generation at IC level verification with the Veloce emulator.

Cadence also announced that the Perspec System Verifier supports the new standard. Cadence says that its customers can confidently adopt the Perspec System Verifier to automate SoC coverage closure and achieve up to 10X improved system-level test productivity.

Breker Verification Systems, the other pioneer of graph-based verification technology, announced support last week.

NetSpeed Systems unveiled SoCBuilder, an AI-powered SoC design and integration platform. SoCBuilder includes a catalog of pre-integrated third-party IP along with application-specific reference designs for AI, automotive, 5G, hyperscale compute and AR/VR. The tool provides a unified design environment for IP, chassis integration, design and verification and uses meta-data to capture the SoC specification and design details including basic floorplan information. It then applies machine learning to find optimum design solutions, drawing from built-in reference designs and an IP catalog with a wide range of pre-integrated critical SoC IP.

IP
Flex Logix launched two new embedded FPGA cores. One, the EFLX4K IO eFPGA core, is designed for networking and applications with many heterogeneous processors where customers need to connect very wide buses with relatively small eFPGAs.

The second, the EFLX4K AI eFPGA core, has been specifically designed to enhance the performance of deep learning by 10X and enable more neural network processing per square millimeter. Its AI-MAC architecture is capable of implementing 8-bit MACs or 16-bit MACs reconfigurably. Both will be available for implementation on any new process node in about 6-8 months.

Moortec debuted an IoT-focused embedded monitoring subsystem with a smaller scale and lower power, targeting TSMC’s 40ULP (Ultra Low Power) process technology. The IP subsystem can physically monitor dynamic and static conditions deep within IoT enabled edge devices and can enable continuous DVFS and AVS optimization schemes.

eSilicon released a configurable 7nm IP platform targeted for networking and data center applications. The platform includes flexible 56G and 112G SerDes, a ternary content-addressable memory (TCAM) compiler, a programmable high-bandwidth memory gen2 (HBM2) PHY, multiple network-optimized memory compilers and extended-voltage general-purpose and LVDS I/Os. The platform is completed with plug-and-play partner IP for functions such as PCI Express PHY, controllers, PLL and PVT monitor.

SiFive debuted two configurable low-area, low-power MCU RISC-V cores designed for use in embedded devices. The E21 provides mainstream performance for MCUs, sensor fusion, minion cores and smart IoT markets, while the E20 is now the most power-efficient SiFive standard core designed for microcontrollers, IoT, analog mixed signal and finite state machine applications. They include a fully configurable memory map, multiple configurable ports, tightly integrated memory (TIM), fast IO access and a new CLIC interrupt controller.

General Processor Technologies added two new IPs to its portfolio. The first is an AI accelerator designed for CNN inference and runs at up to 1GHz in 28nm technology. The second is an optimized Variable Length Vector (VLV) DSP execution unit targeted for digital and image processing.

Sankalp Semiconductor released Embedded DisplayPort (eDP) receiver IP compliant to the eDP 1.4b receiver specification. The IP is developed in 80nm CMOS technology supporting configurable data rates of 1.6, 2.16, 2.43, 2.7 Gb/s. Sankalp also announced a program for post-silicon validation of analog designs comprising both software and design services.

Deals
Arteris IP and Magillem are teaming up on a product integration to accelerate the architectural definition of complex chips. Using the Magillem front-end design environment (MAI, MPA and MRV), users can import Arteris FlexNoC non-coherent interconnects and Ncore cache coherent interconnects using the IP-XACT format.

Kalray is working with OneSpin Solutions to deploy an automated flow for the analysis of hardware architectural metrics required by the ISO 26262 functional safety standard, which Kalray is using to make sure its massively parallel processor arrays can be used in automotive systems.

Vatics adopted Synopsys’ Fusion Technology for its next-generation 28nm, 6-million-instance, multimedia SoCs. Vatics cited a 40% reduction in design closure time. Arbe Robotics selected a range of Synopsys IP including DesignWare ARC EM Safety Island, EV6x Embedded Vision Processor, and STAR Memory System for its new 4D high-resolution imaging radar SoC. Additionally, RIKEN used Synopsys’ ASIP Designer to develop a custom processor for its molecular dynamics simulator, which is used to analyze large biological systems.

Rambus renewed a patent license agreement with IBM. The five-year agreement authorizes IBM to integrate Rambus memory controller and interface technologies.

Rafael Micro licensed Cadence’s Tensilica Fusion F1 DSP for its RT580 narrowband IoT modem IC, which integrates RF radio and includes necessary firmware support. Rafael Micro cited lower power and 45% smaller code size. Xinyi Information Technology also licensed the Fusion F1 DSP for its new Marconi X1 NB-IoT modem SoC, which integrates a CMOS power amplifier in a single die and features an NB-IoT protocol stack from Huachang Technology.

Certifications
Synopsys’ Custom Design Platform has been certified for Samsung Foundry’s 7nm Low Power Plus (LPP) process using EUV. A Synopsys-ready process design kit (PDK) and custom design reference flow are available. Additionally, Synopsys’ RedHawk Analysis Fusion was validated with 100% correlation to ANSYS’ RedHawk IR/EM analysis tool and certified for Samsung Foundry’s 10LPE, 8LPP, and 7LPP processes.

Mentor’s Calibre nmPlatform and Analog FastSPICE custom and analog/mixed-signal circuit verification platforms are available for use in the verification and sign-off of production tapeouts for Samsung Foundry’s 8LPP and 7LPP process technologies.