What Happened To Next-Gen Lithography?

Chipmakers continue to march down the process technology curve. Using today’s optical lithography and multiple patterning, the semiconductor industry is scaling its leading-edge devices far beyond what was once considered possible.

The question is how far can the industry extend 193nm immersion and multiple patterning before these technologies become too expensive? And when will the industry need to make the transition to next-generation lithography (NGL)?

In theory, 193nm immersion could extend to the 7nm logic node and beyond, but there is a catch. It may require octuple patterning and other complex steps, which could be an expensive and terrifying proposition.

“The multiple patterning play is going to be there as far as we can see,” said Dave Hemker, senior vice president and chief technology officer at LAM Research, “but it also comes down to the economics. If you have to go to octo patterning, there might be a spreadsheet out there that says: ‘Maybe there are other ways to do it that are more cost-effective.’”

Today, there is only one lithographic option for chipmakers—193nm immersion and multiple patterning. But clearly, chipmakers would like to insert NGL sooner than later. As before, extreme ultraviolet (EUV) lithography is the leading NGL candidate. Multiple-beam e-beam and nanoimprint are still in the hunt. And directed self-assembly (DSA) is the wild card in NGL.

Needless to say, EUV, multi-beam and nanoimprint are delayed and are not in volume production. DSA is immature. But chipmakers are not throwing in the towel and are still counting on NGL. In fact, NGL is not standing still. Each NGL technology has made some progress recently. Some technologies have made more advances than others. So where is the industry at in NGL?

The leading candidate
Leading-edge chipmakers are still counting on EUV, despite the various delays and setbacks with the technology. Late last year, in fact, ASML Holding shipped its first production-worthy EUV lithography scanner. The 13.5nm wavelength tool, dubbed the NXE:3300B, has a numerical aperture of 0.33 and a resolution of 22nm half-pitch.

Today, there are at least five NXE:3300B systems at customer sites, although chipmakers are still wrestling with various issues with the tools. As of now, EUV will likely miss the 10nm node. Chipmakers are targeting EUV for 7nm, but as before, there are still issues with the EUV source, mask infrastructure and resists.

Still, IMEC, one of the beta site customers for ASML’s EUV tools, said that EUV and the oft-delayed power source are making some noticeable progress. “It’s clear that the power must be increased by a significant amount in order to make EUV competitive,” said Kurt Ronse, director of advanced patterning at Imec. “But in the last couple of months, there has been quite a bit of progress. The power is now at the level where you really can use the system to do a lot of process development. The power is not yet at the level to go into volume production, but there is a clear roadmap to get there in the next one to two years.”

Until recently, the EUV source generated less than 10 Watts of power, which made EUV lithography impractical for mass production. By the end of 2013, chipmakers hoped that the EUV source would generate 80 Watts of power, which equates to an overall EUV throughput of 58 wafers per hour.

To date, however, the EUV source has not quite reached those desired levels. “We are in the several tens of Watts,” Ronse said. “It’s on the order of 40 or 50 Watts. But these numbers are changing day by day now. Of course, the next question is what is the reliability level? And what is the uptime of the system?”

Many of these and other questions remain unclear right now. Another issue is that EUV was supposed to bring the industry back to single exposure. That won’t necessarily be the case if EUV is inserted at 7nm. “By that time, you will need multiple patterning with EUV,” said Lam’s Hemker.

On the memory front, NAND flash and DRAM makers are moving full speed ahead without EUV. “The DRAM industry is marching towards 10nm,” said Gill Lee, senior director and a principal member of the technical staff at Applied Materials. “Major DRAM players are not counting on EUV in the near future. Basically, the DRAM industry is adopting more multiple patterning technologies at different levels. That allows the DRAM guys to move below 20nm.”

The other contenders
For years, Intel and TSMC have been bullish about multi-beam, electron-beam for direct-write lithography applications. But as it turns out, multi-beam for direct-write still has a long way to go before it can process wafers in a production fab.

But two vendors, Mapper Lithography and Multibeam, have separately made some incremental progress with the technology. For example, Mapper recently installed the world’s first pre-production multi-beam e-beam tool at CEA Leti. The French-based R&D organization also showed the first images with the tool, dubbed the Matrix 1.1.

Initially, the Matrix 1.1 achieved 42nm half-pitch lines and spaces. “This is a starting point,” said Laurent Pain, lithography lab manager at CEA-Leti. “We should be able to expose more and more wafers as time goes on.”

The current Matrix 1.1 tool consists of 1,300 individual beams, but only 50% of those beams were operating during the first exposures. By year’s end, Mapper and CEA-Leti hope to have all 1,300 beams operating within the tool. “To go to 1,300 beams, you need a good source, blanker and projection lens,” Pain said.

The blanker is an active MEMS component, which will help boost the beam count for the Matrix tool. The blanker and other components for the tool will be manufactured in a new plant in Moscow, Russia. Mapper and its Russian investor, Rusnano, are the venture partners in the plant.

Still, Mapper may have some difficulties in terms of reaching its ultimate goal with the Matrix 1.1. The company hopes to achieve 10 wafers per hour with a 13,000-beam tool by 2015.

Mapper and other multi-beam e-beam hopefuls face some challenges. “It looks simple on paper,” said Imec’s Ronse. “But in reality, it’s extremely complex. All of these beams have to be perfectly synchronized with each other. And, of course, all of these electrons are basically disturbing each other. And the faster you try to write, the more these effects will occur. So any decent throughput on the wafer with multi-beam is going to be very complex.”

While Ronse is pessimistic about multi-beam for direct-write applications, he sees a bright future for the technology in the photomask arena. In fact, the team of IMS Nanofabrication and JEOL are readying the industry’s first multi-beam mask writers in the market. Targeted for the 10nm node, the tools combine IMS’ multi-beam technology with JEOL’s platform. The first systems are expected to ship in 2015.

“Today, masks are written with single beams. And for 14nm, 10nm and 7nm, the writing times for these critical levels on masks are becoming way too slow. We are talking about 20 hours in many cases,” Ronse said. “So in mask production, you can have a much simpler system with multiple beams, which can write in parallel. In mask production, the dimensions are four times bigger. So you have less repulsive forces between these electrons.”

Meanwhile, another NGL technology, nanoimprint, is beginning a new chapter. Canon recently acquired the semiconductor unit of Molecular Imprints (MII), a supplier of nanoimprint tools. That group is called Canon Nanotechnologies (CNT).

CNT is developing a new, modular nanoimprint tool. The first tool is a single module system. The tool has demonstrated 15nm half-pitch images, with a 5nm overlay and a throughput of 20 wafers per hour. CNT will provide more details about the tool in 2015, according to Doug Resnick, vice president of marketing and business development at CNT.

Another technology, DSA, is the dark horse in the NGL race. DSA is not an NGL tool per se, but rather it is a complementary technology. DSA is used with 193nm scanners and specialized track gear. When used in conjunction with a pre-pattern that automatically directs the orientation of the block copolymers, DSA can reduce the pitch of the final printed structure.

DSA is gaining momentum in the market. GlobalFoundries, IBM, Intel, Samsung and TSMC are all working on DSA in R&D. The consensus among chipmakers is that DSA could be ready for high-volume manufacturing at 7nm or 5nm.

DSA faces some challenges. “Today, it has to be demonstrated that DSA can indeed be integrated in a normal CMOS flow and come out with defect levels that are acceptable,” Imec’s Ronse said. Imec itself has a 300mm DSA pilot line in its R&D fab.

“The defect levels are going down gradually (for DSA). Every six months, we see an improvement in defectivity. But today, we are still too high in terms of defects for DSA. That’s going to take a few more years, at least one to two years to bring the defectivity down,” Ronse said. “Another aspect is EDA. DSA is a chemical process. So you cannot tell those block copolymers where to form a contact hole. That means in the design world, people may have to come up with DSA-friendly designs. The EDA suppliers like Mentor and Synopsys are working with us to see how we can start from the current cell layouts and how we can slightly modify them to make them more DSA-compatible or friendly. Ultimately, the designs will have to be taught by the software what to do and what not to do.”

Today’s DSA materials are based on PS-PMMA technology, which could hit the wall at 12nm or 11nm. To go beyond 10nm, the industry is working on next-generation high chi materials. “They are much less mature in terms of chemistry and the annealing processes, as compared to PS-PMMA,” he said.

So until DSA and the other NGLs are ready, the industry must extend 193nm immersion and multiple patterning. “EUV is not there yet. DSA is not really mature enough,” Ronse said. “So multiple patterning is the only option today. That means many extra deposition and etch steps. Memory companies are already doing that, but that’s extremely expensive. Everybody would like to get rid of that.”