What’s After 10nm?

For some time, chipmakers have roughly doubled the transistor count at each node, while simultaneously cutting the cost by around 29%. IC scaling, in turn, enables faster and lower cost chips, which ultimately translates into cheaper electronic products with more functions.

Consumers have grown accustomed to the benefits of Moore’s Law, but the question is for how much longer? Chips based on today’s finFETs and planar fully depleted silicon-on-insulator (FDSOI) technology are expected to scale down to the 10nm logic node.

Now, chipmakers are evaluating and defining the transistor options for the 7nm logic node, slated for the 2017-2018 timeframe, with 5nm in the exploratory phase. Many chipmakers even see a scaling path to 3nm, which is nearly a decade away.

But at 7nm and beyond, there is still no consensus on which transistor technology will keep the industry on the traditional cost-per-transistor curve. Staying on the curve will be a tall order. Today, in fact, there are troubling signs that the cost-per-transistor curve is slowing at the 20nm node and potentially at 14nm, which may derail Moore’s Law and impact the price/performance of new chips.

So, one of the challenges for chipmakers is to get the cost-per-transistor curve back on track. In the near term, finFETs and planar FDSOI appear to be viable solutions. But at 7nm, chipmakers have narrowed down the choices and are now evaluating four or so basic contenders—III-V finFETs; gate-all-around finFETs; nanowire finFETs; and SOI finFETs. For 5nm and perhaps 3nm, the industry is looking at these technologies plus tunnel FETs (TFETs).

Meanwhile, instead of scaling, the other path is to go vertical with 2.5D/3D stacked die and monolithic 3D. And in the distant future, there are several exotic technology options, such as carbon nanotubes and graphene.

One chipmaker put the challenges in perspective. “We are expected to do even better on a two-year cadence forever and ever,” said Michael Mayberry, corporate vice president of the Technology and Manufacturing Group and director of components research at Intel. “From a technology point of view, we have more choices than ever. That’s a good thing. That means we have a job. It also means we have more work to do. So, we need to choose wisely what we need to work on.”

Even the large companies with deep pockets don’t have the time or resources to work on all transistor technologies. The eventual winners and losers will be determined by cost, manufacturability and functionality. “It’s not a question which technologies are better,” Mayberry said. “The question is which one can you build.”

Evaluating the options
By 7nm, or perhaps sooner, chipmakers will likely need to develop more than one of the futuristic chip architectures. By then, however, there may not be a one-size-fits-all chip technology that meets all of the necessary requirements for future systems. “There won’t be a single device in the roadmap at that point that gets all of the action,” said Jo De Boeck, chief technology officer at Imec. “We see a bifurcation of technologies based on performance and low power.”

De Boeck sees a future scenario where chipmakers will require both leading-edge transistor types and 3D devices. “It’s not an either/or scenario,” he said. “Our view is that chipmakers will develop these technologies hand-in-hand. 3D will be part of the systems solution.”

All of the futuristic technologies have several challenges. “Gate-all-around with a vertical pitch looks very interesting. But if we talk to designers (about gate-all-around), they will go crazy. They don’t need to know how to design with all of these features,” he said. “The (III-V finFETs) are still on the roadmap, but they are not manufacturable yet.”

So, the question is which future chip architecture candidates will move into production and which ones will get left behind. For some time, chipmakers have been weighing the various options, and narrowing them down. “When we look at any node, we look at four buckets—physical, electrical, reliability and cost,” said Srinivasa Banna, a fellow and principal member of the technical staff at GlobalFoundries.

The physical bucket involves lithography and new materials. Electrical involves device isolation. Reliability is self-explanatory. “The innovations might be there, but it must be practical in terms of cost,” Banna said.

Based on those metrics, GlobalFoundries can make some reliable assessments. “Moore’s Law will continue to 7nm. Beyond that, it’s likely,” he said. “For the device architecture, we see that the finFET will extend to 7nm. For that, we will likely need high-mobility channel materials. We are thinking in terms of silicon-germanium, germanium or III-V.”

By then, the industry will require new breakthroughs in lithography, interconnects and new materials. “EUV, for example, is needed at 7nm,” he said. “But if EUV is not there, then there are other solutions. We can use (multiple) patterning. There are known optical solutions.”

Adam Brand, senior director of the Transistor Technology Group at Applied Materials, agreed. “There is demand for more transistors. Even though complexity is rising, I would argue that we can continue to use these known solutions and use engineering to drive the costs down to keep Moore’s Law going,” Brand said.

7nm/5nm transistor candidates
Meanwhile, today’s finFETs and FDSOI technologies are expected to last until 10nm. “Then, by 7nm, the traditional finFET will start to run out of steam,” said Aaron Thean, program director for logic devices at Imec. “The scaling of the gate length just drives the electrostatics to a bad place. That means we have to fundamentally change the device structure again.”

For 7nm, the leading transistor candidate is the high-mobility finFET. In this technology, the finFET is injected with III-V materials in the channels to boost the mobility. The first high-mobility finFET will likely consist of germanium (Ge) in the PFET and tensile silicon in the NFET. Ge has nearly four times the electron mobility compared to silicon.

Then, at 5nm, the industry may move to a next-generation high-mobility finFET. The leading candidate is Ge for PFET and indium-gallium-arsenide (InGaAs) for NFET. “The race is not completely over yet,” Thean said. “For NFET, you have silicon contending with III-V. On the PFET side, you have more options.”

The high-mobility finFET is not the only option, however. Moving into contention at 7nm and 5nm is the gate-all-around finFET. Considered the ultimate device in terms of electrostatics, the gate-all-around can have two or more gates, which are wrapped around by III-V nanowire channels. In one example, Samsung recently demonstrated a gate-all-around finFET at 3.8nm.

“There are different pathways the industry can go,” said Applied Materials’ Brand. “The most likely pathway is a gate-all-around structure. There are already demonstrated devices down to a gate length. That means that there are already demonstrated working transistors suitable for below the 4nm node, maybe the 3.5nm node.”

Making such a device is easier said than done. The challenges are the contact materials and how to make the nanowires with high mobility surfaces. “To scale these CMOS devices, we will need to scale the fin width down to a 5nm gate-all-around structure,” Brand said. “They will have n and p channels. We will need to be able to dope the structure to make junctions. So, we will need to use conformal doping techniques.”

Another technology candidate, the SOI-based finFET, also is gaining ground. For example, IBM is working on one technology, dubbed “aggressively scaled strained-silicon directly-on-insulator (SSDOI) finFETs.” SSDOI finFET is somewhat similar to an FDSOI-based device, said Ali Khakifirooz, an advisory engineer and a scientist at IBM. “The only difference is that the starting wafer is a strained-silicon layer bonded to oxide, as opposed to relaxed silicon bonded to oxide in conventional SOI wafers. So, the wafer as received from a wafer vendor has tensile strain built in the SOI layer,” Khakifirooz said.

“We have the PFET solution. It is not tensile strained silicon. The strain in SSDOI is independent of the device pitch,” he said. “Of course, it is too early to say what a 5nm technology will look like. But as far as the strain and the NFET performance boost is concerned, SSDOI is able to fit the bill.”

Meanwhile, there is another SOI-like option—the tri-gate silicon nanowire MOSFET. “What is the solution for 7nm? The nanowire,” said Toshiro Hiramoto, a professor at the University of Tokyo. “However, it’s not the conventional gate-all-around nanowire. My answer is a nanowire with back-bias control. Back bias is necessary to handle the variability and the power management.”

Beyond CMOS
Researchers are also looking at various technologies beyond classical CMOS, which could appear in the next decade or beyond. “In terms of mobility, strained-silicon gets you a 3x performance improvement,” Intel’s Mayberry said. “Germanium and III-V give you another 10x. But carbon nanotubes and graphene are actually the highest mobility materials known today.”

Besides graphene and nanotubes, researchers are also taking a hard look at non-charged, spin-based technology. “Two technologies—spin torque majority gate and all spin logic—have interesting aspects. They can do multiple inputs to get a single output. Maybe it takes 40 elements to do things with transistors, but it only takes five to do it with magnetic logic,” Mayberry said. “Spin torque domain wall and spin wave devices are ones, in principal, that can do multi-level logic.”

All of the futuristic CMOS and non-CMOS solutions look promising, at least in the lab. “We’ve already built 5nm devices and smaller,” he said. “They don’t necessarily work that great, but we know we can go smaller than that. The ability to control them is more of the limitations of the physics. There is a lot of variability in the devices in the lab. We need to figure that out before we go into production.”