Advanced etch holds key to nanosheet FETs; evolutionary path for future nodes.
After nearly a decade and five major nodes, along with a slew of half-nodes, the semiconductor manufacturing industry will begin transitioning from finFETs to gate-all-around stacked nanosheet transistor architectures at the 3nm technology node.
Relative to finFETs, nanosheet transistors deliver more drive current by increasing channel widths in the same circuit footprint. The gate-all-around design improves channel control and minimizes short-channel effects.
Fig. 1: In nanosheet transistors, the gate contacts the channel on all sides (gate all around) and multiple sheets enable higher drive current than in finFETs. Silicon orientation differences (110 to 100) changes the carrier mobilities in the channel. Source: K. Zhao, IBM/IEDM Tutorial 2021
Superficially, nanosheet transistors resemble finFETs, but nanosheet channels are aligned parallel, not perpendicular, to the substrate. Nanosheet transistor fabrication starts with deposition of a Si/SiGe heterostructure, isolated from the substrate to prevent parasitic conduction.
A first patterning step cuts this heterostructure into pillars. After dummy gate fabrication, an inner spacer etch step cuts a recess in the SiGe layers. The inner spacer etch step (discussed in more detail below) is a critical process step, because it defines the gate length and the source/drain junction overlaps. Once the inner spacer is in place, source/drain epitaxy, a channel release etch, and formation of the replacement gate complete the transistor.
Building transistor pillars
Even though the SiGe layers are sacrificial material — not part of the finished device — their germanium concentration is an important process variable. As Nicolas Loubet and colleagues at IBM and TEL explained in work presented at the 2019 IEEE Electron Device Meeting, increasing the amount of germanium increases the SiGe lattice constant, which in turn increases lattice strain in the silicon layers, potentially introducing defects.[1] On the other hand, completely removing the SiGe material without damaging or eroding the silicon requires an etching process with high SiGe:Si selectivity. Reducing the germanium concentration tends to reduce selectivity.
Ideally, device designers would like to minimize the spacing between nanosheets in order to reduce parasitic capacitances. There are practical limits to the manufacturable spacing, though, as IBM researcher Kai Zhao explained in a tutorial session at last year’s IEDM. Once the sacrificial SiGe is gone, the space between nanosheets needs to accommodate residue removal, the gate metal, the gate dielectric, and (especially for pFETs) any additional work function adjustment layers.
After Si/SiGe heterostructure deposition, an anisotropic etch cuts pillars of the desired width. In finFET architectures, fin width is standardized, in part due to the limitations of lithography schemes that depend on pitch-doubling. The adoption of extreme ultraviolet lithography gives designers more flexibility to use variable device widths as needed.
Naoto Horiguchi, imec’s director of CMOS device technology, explained in an interview that nanosheet transistor pillars can be wider than finFET fins. Further, the width of a stacked nanosheet transistor is the sum of its component nanosheets. As a result, the variability of the pillar width is typically small relative to the total channel width.
Fig. 2: The etch profile directly affects transistor behavior and consistency in device operation. Source: IBM Research
Because Si and SiGe have different etch characteristics, etching through alternating Si/SiGe layers is a more complex task than etching a monolithic silicon pillar. Eric Miller, manager for plasma etch research at IBM Research, explained that electrically, each layer in a stacked nanosheet device functions as an independent transistor. If the etch profile of the stack is not vertical, the dimensions and characteristics of the component devices will vary.
Further, Horiguchi noted that, as when etching silicon, the process needs to balance etching and sidewall passivation. Exposed SiGe surfaces tend to be less stable than silicon.
Defining the channel
Once the nanosheet pillars are defined, a highly selective isotropic etch creates the inner spacer recess, indenting the SiGe layers relative to the silicon nanosheets. This spacer defines the gate length and junction overlap, Loubet said, both of which are critical transistor parameters that help define the tradeoff between device resistance and capacitance. The shape of the indentation defines the separation between the remaining SiGe — which ultimately will be replaced by the gate — and the source/drain regions. Wet chemistry etch processes tend to leave half-moon profiles, as a meniscus forms between two adjacent nanosheets. Removal of the remaining SiGe during the channel release etch can expose the source/drain and place them in direct contact with the gate metal.
Fig. 3: Critical etching steps in the nanosheet transistor process flow include dummy gate etch (b), anisotropic pillar etch (c), isotropic inner spacer etch (e), and the channel release step (g). Source: N. Loubet, IBM
While dry etch processes leave no meniscus, Yu Zhao and colleagues at Hitachi still observed a rounded etch front. In work presented at last year’s IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Hitachi researchers used STEM-EDX to measure germanium concentration, identifying a germanium-rich layer on the sidewalls of their Si/SiGe pillars. The layer, which apparently formed during the anisotropic pillar etch, etched more quickly, leading to a rounded etch front. Then, as the etch proceeded through this sidewall region into the bulk SiGe material, with a uniform germanium concentration, the uniform etch rate preserved the existing etch front shape. Further optimization of the pillar etch resolved the problem.[2]
The last new process module in nanosheet devices, the channel release etch, defines the final nanosheet thickness. While the semiconductor industry is very capable of depositing precisely controlled and uniform heterostructures, maintaining such precise control while etching the SiGe away presents some new challenges. Consistent transistor performance requires extremely uniform nanosheets, Loubet said, typically with 0.5nm or less of silicon loss.
EUV lithography allows designers to specify variable device widths, but they rely on the channel release etch to actually achieve them. If the channel release etch is not selective enough, the silicon nanosheets in narrow devices will erode before the channels in wider devices are cleared. Because etch selectivity depends on germanium concentration, germanium residue and germanium diffusion during the pillar or inner spacer etch can lead to silicon loss during the channel release etch.
Moving beyond nanosheets
Even as the first nanosheet devices make their way to production, manufacturers are already considering enhancements for future scaling. Imec’s forksheet design, for instance, places an insulating pillar between the n-channel and p-channel halves of an nFET/pFET pair. The improved isolation reduces the minimum spacing between the two, and therefore the overall circuit footprint.
IBM’s Kai Zhao noted that unique device mobility concerns arise because the nanosheet architecture places the (100) crystal plane parallel to the substrate, as opposed to the (110)-oriented channel in finFETs. Using the (100) plane changes both the absolute and relative mobilities of electrons and holes.
Table 1: Carrier mobilities in silicon finFETs and nanosheet FETs. Source: Kai Zhao, IBM/IEDM Tutorial, 2021
One proposal to improve hole mobility, described by R. Bao and colleagues at IBM at last year’s IEDM, uses silicon channels for nFETs and SiGe pFET channels. The nFET nanosheet stack alternates silicon and SiGe, while the pFET stack uses SiGe channel layers with SiGe sacrificial layers. Separation between the two depends on the germanium sensitivity of the etch process.[3]
An alternative approach, demonstrated by Wei-Yuan Chang and colleagues at Taiwan Semiconductor Research Institute, relies on Si/SiGe stacks for both nFET and pFET devices. In this approach, a mixture of hydrofluoric acid, hydrogen peroxide, and acetic acid removes SiGe from stacks destined to become nFETs, achieving a selectivity of about 79:1. TMAH solution was used to remove silicon from stacks that will become pFETs, achieving about 8:1 selectivity. These early results were promising, they said, but further optimization of the pFET etch is needed.[4]
Further scaling of nanosheet transistors will require even more drive current in the same or smaller circuit footprint. To that end, Sylvain Barraud and colleagues at Leti demonstrated both nFET and pFET devices with seven silicon channels, instead of the more typical two, tripling the available drive current.[5] Even further in the future, possible designs include complementary FETs (CFETs), in which a single nanosheet stack contains both p-type and n-type channels, and vertical transport nanosheet FETs (VTFETs), which position the nanosheets perpendicular to the substrate plane.
Whatever the future holds, it’s clear that the industry is in no hurry to abandon silicon, despite the theoretical advantages of alternative materials.
References
Related Reading
Transistors Reach Tipping Point At 3nm
Nanosheets are likeliest option throughout this decade, with CFETs and other exotic structures possible after that.
Stacked Nanosheet And Forksheet FETs
Next-gen transistors will continue using silicon, but gate structures and processes will change.
New Transistor Structures at 2nm/3nm
Gate-all-around FETs will replace finFETs, but the transition will be costly and difficult.
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