Chipmakers Look Beyond Scaling

GlobalFoundries CTO Gary Patton digs into how customers’ priorities are shifting with new market opportunities.

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Gary Patton, CTO of GlobalFoundries, sat down with Semiconductor Engineering to discuss the rollout of EUV, the rising cost of designing chips at the most advanced nodes, and the growing popularity of 22nm planar FD-SOI in a number of markets. What follows are excerpts of that conversation.

SE: You’ve just begun deploying EUV. Are you experiencing any issues?

Patton: It’s a very complicated tool. There are challenges in getting everything set just right.

SE: What size power supply are you using?

Patton: We’re running at 150 watts right now.

SE: There are reports in papers and conference presentations about stochastic effects and photoresist-related problems. How does that affect your rollout?

Patton: We’re going to start with contacts and vias, where mask defectivity is not critical. Then we’ll extend it to metal lines. We’re adding it in a very transparent way. Our customers will get the benefits that hopefully will be expected of EUV in terms of defectivity and throughput, but our plan is not to use EUV in any critical path at 7nm.

SE: Along with the cost of EUV, there’s been a lot of discussion about the cost of designing chips at 7nm and 5nm. Lithography is just one factor there. Will companies be designing full chips at 3nm, or will they start doing the logic at the most advanced node and the analog at 40nm, for example?

Patton: I’ve been a long-time advocate of 2.5D and 3D integration. It’s coming now for real. 2.5D, in particular, has taken off on 14nm. A large portion of our ASIC design wins are leveraging 2.5D. We also have some pretty exciting projects on 3D at 7nm. They will do some of this disaggregation you’re talking about. So you can have a logic chip and then layers of SRAM above it.

SE: The initial idea was that this would be logic on logic, but that was before anyone started considering thermal issues. Is that still coming, or is the future about memory on logic?

Patton: I see it as more likely with logic and memory above it. Not everyone can afford to go into these advanced nodes, though. We’re seeing the node-to-node transition slowing down. There are still some companies focused on the Christmas season and driving hard to move from node to node, but the value proposition is becoming weaker. Both 10nm and 20nm were very weak nodes from a customer perspective. Customers skipped those and went to 14, or they’re now heading to 7nm. I see similar things playing out at 5nm as at 10nm and 20nm. In addition, that will be the end of the road on electrostatics for a finFET device.

SE: So where do you go next?

Patton: I don’t know what our next node will be called, but we’re not going to do a half-node. Our 7nm is a very strong shrink off of 14nm, with a strong performance improvement, and we’re looking to do the same thing after 7nm.

SE: How many companies can afford that?

Patton: It’s very expensive to design a chip at the latest node with all the masks. It’s 85 masks. There are a number of articles that have been published where the cost of designing a chip is several hundred million dollars and growing. That’s where FD-SOI comes in. It’s a much lower cost to design an FD device. There are fewer masks. Not all of that is double or triple patterning. It’s really optimized for cost both from a technology and a design perspective. And for customers looking for that balance between power, performance and cost, and the ability to integrate RF on the same chip, FD plays well in that market.

SE: How does that stack up against finFETs?

Patton: It doesn’t compete with finFET. It’s a recognition that the market requirements have expanded with this move to connected intelligence. There’s a more diverse set of requirements from a customer perspective. FinFET doesn’t cover it all. We were the first to recognize that. Our competitors had to follow us into this space with their own 22nm offerings, but the advantage we have is our 22nm was optimized for this space. We didn’t take a 22nm off the shelf and try to jury-rig it to operate it in this low-power, battery-powered mobile space. It was optimized for this space.

SE: What’s the advantage of using FD-SOI for RF?

Patton: Planar devices are far superior to finFET devices in RF. If you’re trying to do millimeter wave or 5G type of applications where you need high-performance RF devices, FD-SOI is a winner. And that’s where we’re seeing a lot of our customer traction. It’s happening in automotive for millimeter-wave radar. It’s happening in IoT, where customers are trying to put more intelligence on the edge, and at the same time they need to be able to communicate. You can take a five-chip solution down to one chip with 22nm FD-SOI. And then there’s the whole machine learning market.

SE: Why is planar superior to a finFET?

Patton: For RF, it’s because of the vertical resistance and capacitance of a finFET.

SE: Does that improve if you move to vertical or horizontal nanowire? Or is that just slicing up the finFET?

Patton: No, it’s not going to get any better. So there’s a fundamental advantage of FD in that millimeter wave space. We’ve had 36 design wins at 22nm. All of them have RF in their product. A lot of them have RF integrated on a single-chip solution. It’s one of the compelling value propositions of this technology.

SE: IoT as a concept is now breaking up into lots of vertical markets, rather than a single technology approach. But there is a lot more intelligence going into the edge. How much of this is happening with FD-SOI versus the most advanced node?

Patton: The areas where we’ve gotten design wins are in cryptocurrency, edge IoT devices—some of them for machine-learning applications—5G and automotive. And they’re all FD.

SE: Why is cryptocurrency moving to FD-SOI?

Patton: Power is a big issue. You need to be able to do that computing at very low voltages. And you can boost performance when you need it with body biasing.

SE: The numbers being tossed around for crytocurrency mining are somewhere in the neighborhood of 3% to 4% of the world’s energy.

Patton: It’s an incredible market opportunity for us.

SE: Do you expect much competition from planar CMOS?

Patton: Our customers have benchmarked our FD technology against the competition and come out with same answer. One of the things we can do with FD-SOI is stack the devices in a power amplifier. That’s a really compelling solution for power amplifiers. You can lay out the design and stack the transistors because of the FD-SOI substrate insulation, and make a very compelling power amplifier. You can’t do that with bulk.



1 comments

realjj says:

If you define the packaging solutions by contact pitch, you realize that there is scaling here too. Hundreds of um with PoP , tens of um with FOWLP, single digit with W2W bonding and so on. It ends up as monolithic 3D when contact pitch reaches sufficient dimensions and it enables another type of scaling, on the vertical.
So this is not “beyond scaling”, it’s just another type of scaling.

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