Wrestling With Analog At 3nm

Analog engineers are facing big challenges at 3nm, forcing them to come up with creative solutions to a widening set of issues at each new process node. Still, these problems must be addressed, because no digital chip will work without at least some analog circuitry.

As fabrication technologies shrink, digital logic improves in some combination of power, performance, and area. The process technology is optimized for these. Yet analog basically has to accept what it gets. With each process shrink, voltages go down, the number of parasitics goes up, and noise and variation increase. New techniques, such as gate-all-around, impact flexibility, and analog engineers often have to reinvent how they do things just to maintain the same functionality, sometimes at the expense of area.

At a minimum, there will be some type of interface or peripheral for every SoC. “There will be a SerDes for PCI Express or USB or any type of communication,” says Hany Elhak, group director for product management and marketing at Synopsys. “The chip will probably be talking to memory, and that would require something like DDR or HBM, which is another complex analog block. All these big digital SoCs will include embedded SRAM, and that’s an analog circuit. Analog is an integral part of any SoC, and if the SoC is going to 3nm, analog is going 3nm. The issue is that all these advanced nodes are designed for digital. Analog designers need to jump through hoops to make things work.”

Fig. 1: The increasing role of analog in designs. Source: Synopsys

It requires different ways of thinking. “While it is a digital process, analog designers are finding ways to apply those techniques to build analog blocks,” says Jeff Johnson, senior solution architect at Cadence. “In some cases, they will build in more calibration. Process variation has become so large, and digital logic is so cheap, that you can add calibration loops or do things differently.”

Whether that is practical is another matter. “We are taping out our PCIe and PHY in N3 early next year, so we have done those designs,” says Priyank Shukla, staff product marketing manager at Synopsys. “Analog designers always come up with innovative circuit solution to the process problem. In analog design, one of the important parameters of interest is power supply voltage, which is going down to 1.4 volt, instead of 1.5 volts. We worked around those constraints and came up with new architectures. Another big issue for analog design is matching. Each transistor is behaving individually, and you have to match two transistors for their performance.”

Minimum analog building blocks
For digital, there is a short list of primitive gates, registers, and memories from which all designs are constructed. Analog has a similar set of fundamental blocks. “The fundamental blocks for analog are things such as band gaps, op amps, PLLs, comparators, digital-to-analog converters (DACs), and analog-to-digital convertors (ADC),” says Cadence’s Johnson. “If you have those building blocks, you can do a number of things with them. For example, A SerDes is made up of PLLs, band gaps, comparitors, and ADC.”

Some of these blocks are becoming more challenging. “The band-gap circuit is a crucial block, which provides a constant voltage to the whole SoC,” says Synopsys’ Shukla. “In previous generations, this band-gap is the band-gap voltage of silicon, which is 1.2 volts. At the 3nm process node, the supply itself is very close to that, so you need a new design to create a constant reference voltage in your SoC.”

There are many other blocks necessary to provide the functionality that digital circuits expect. “There is power management that requires ac/dc converters and other analog circuits,” says Synopsys’ Elhak. “Chips interfacing with sensors will need ADCs. There will always be the need for the PLLs for clock generation on digital SoCs. The PLL is a very important block that needs to be included in any SoCs today, even if it’s a pure digital.”

But not all analog functions can be built economically in the latest nodes. “Area does not scale for analog blocks in the same way as digital,” says Sathishkumar Balasubramanian, head of product management at Siemens EDA. “For example, a 100 ohm polysilicon resistor, which sustains a certain current, will have approximately the same size in a 28nm process as it had in a 180nm process. Or the size of an inductor used in an LC oscillator is also not going to scale down.”

Re-architecting
Matching always has been an important capability for analog. “You would make big, wide, long gate-length devices to try to get matching,” says Johnson. “As the processes change, you just change the way those things work, and you can actually save area by using what we call stacked gates to come up with your matching function. Or I can insert an ADC to calibrate something. It may be a lot smaller than trying to build a differential pair so big that it matches in all of the corners that I want. By the time I did that, the amount of power it would probably take, and the area would be so big, it wouldn’t be practical.”

Variability is creating a lot of challenges. “That means you have to run more Monte Carlo simulations,” says Elhak. “It also means that designers need innovative architectures to calibrate for process changes. These could be digital loops, or even software loops that add to the complexity of the analog circuit. One of the big innovations in EDA is variability analysis, high-sigma Monte Carlo, using machine learning to run Monte Carlo analysis faster. These are all important areas from the tools perspective to address this variability issue.”

Getting to first silicon
Until you have silicon in hand, there is a certain level of trust that has to be placed in models and tools. “It all starts with the PDK, and you have to trust the PDK and the tools,” says Shukla. “As a SerDes designer, I can do correlation once I have silicon. This is between what I designed and the analog performance I actually see. Until then, I trust the PDK that the foundry provides.”

Those PDKs evolve over time. “The foundries have a very specific way of releasing them and how they number them,” says Johnson. “Even after they go to what’s called a production release, they often find that something has changed, or they are not getting the yield they want, so they make dramatic changes to the point where device performance changes significantly compared to what you started with. It starts off being a very theoretical thing. And then as they get more data, they tighten those things up.”

That first proof of concept is important. “There is some initial work that is done when the PDK is developed, where the foundry tapes out some silicon,” says Elhak. “It will have some transistor, it will have some gates and other circuits, and based on that the PDK models are refined. From the transistor model, you run SPICE simulation to characterize the digital gates building models for delay, noise and leakage that is used later in the cycle for place and route, timing and power sign-off. But it all starts with defining the PDK. A tool company and the foundry work together and do transistor-level correlation with initial silicon. We have confidence in the team and the process that develops the PDK.”

More work can be done upfront compared to the past. “Some customers are not able to wait for this validation process of the device models and the PDK,” says Elhak. “That’s where TCAD comes into the picture. There are simulation teams working with the TCAD team in what is called TCAD design co-optimization. The standard flow starts with TCAD to develop the process and define the device models. That is used to actually build prototypes, and then using the developed device models to run circuit simulations.”

Game changers
As the industry moves toward 3nm, it is not only process changes that analog designers have to contend with. New transistors are coming into play along with other changes. “The next game changer is gate-all-around (GAA) transistors,” says Andy Heinig, group leader for advanced system integration and department head for efficient electronics at Fraunhofer IIS’ Engineering of Adaptive Systems Division. “It’s not clear if all foundries will start using them at 3nm, but if they come, analog blocks are very difficult. All the transistors must be implemented in a very regular grid, which makes it difficult to get the right sizing for analog components.”

GAA does have a silver lining. “GAA actually helps to control the threshold voltage of the transistor,” says Shukla. “You have better control over the performance of the transistor. But the length of the transistor is limited because you are covering the transistor from all sides. Different performance transistors can be achieved with different width and length ratios. These are the two parameters an analog designer has in this toolbox.”

And depending upon how the technology is implemented, other choices are possible. “You now have a new way to create parallel devices,” says Johnson. “You have the option of using fingers or going up higher in the stack. It will allow for some pretty nice compaction, and some great transistor performance.”

But there are downsides. “With GAA, the capacitance increases,” says Shukla. “And you have capacitance not only between gate and drain, but bulk and drain, etc. That becomes difficult to compensate for. When you have just one control gate, you have parasitic capacitance, which could be understood easily. But now with GAA, that capacitance and its compensation becomes a problem for analog.”

Another potential change on the horizon is buried power rails. This moves the power rails to the backside of the wafer, with vias through the wafer to deliver the power. “The beauty is that it frees up metals on the front side of the wafer for routing,” says Johnson. “It also eliminates a lot of parasitics. Resistance has increased due to the shrinking of the lines, and when you have a lot of them, and power and ground has to be routed, you end up with a whole bunch of capacitances. This fixes a lot of those. You can really cut the capacitance by keeping the power and ground away from the high-speed signaling. And if you need to, you can make the wires wider to get the resistance down without paying a big capacitance penalty. I see a lot of theoretical benefit from it, but in some cases it’s the practicality that matters. What does it really look like when you implement it?”

Foundry divergence
With the introduction of these new technologies, it is unlikely that all foundries will adopt each technology at the same time, or in quite the same way. Literature in the industry suggests this will be very evident with GAA and with buried power rails. This puts an extra burden on IP developers because they have to customize, or even redesign, their analog blocks for each process.

“Each foundry provides different PDKs, and in analog that makes things more difficult,” says Shukla. “Consider matching, where one foundry will have one way of ensuring the matching between two transistors, but another foundry will have their own way. It means we need different techniques to address these challenges offered by different processes. We have come up with some best practices, and we have experience as an IP vendor, so it’s easier for us. But for a company that is focusing on one process node from one foundry, if they were to design across boundaries they will find it challenging.”

That may mean compromise. “We try to standardize everything as much as we can,” says Johnson. “In 28nm, we went to a row-based methodology. And in that methodology, we limited the options designers had when they were making their design. They couldn’t pick any gate length they wanted, they couldn’t take any widths they wanted. We gave them a table that showed the choices. This limited their options and normalized a lot of the foundry differences. As part of our methodology development, we would look at the process, and we would come up with what we thought were the right numbers for the IP we were doing, such as SerDes and DDRs, then standardize that. I envision that’s the exact same thing we’re going to have to do with the GAA. At some level you can break it down to the device performances and then try to standardize what you offer to the circuit designers to use based on that standardization.”

This is becoming a more important consideration. “Many customers are adopting multi-fab strategies because they cannot guarantee capacity from one fab,” says Elhak. “The technologies are diverging between foundries, which means that analog designers need to create different designs, even for the same chip, in order to be able to be fabricated in multiple fabs. This constraint is even bigger for IP providers, which now need to create the same IP on a large number of process nodes.”

Analysis and verification
The size of verification teams has risen much faster than the size of design teams. “The processes have become very complicated and the number of parasitics has increased significantly,” says Johnson. “If you have 100 nodes, each one of those can vary independently. Not only can each node vary, but the parasitics within each node can vary. You need to do simulations that encompass all of that. But even those simulation models are only so accurate. You’re trying to run so many simulations over so many corners, and it takes a long time.”

Circuit sizes also are growing. “With these advanced nodes, there are limited possibilities for controlling the size of transistors,” says Elhak. “This requires more transistors to be used and stacked. Plus, the innovative architectures that are needed to deal with the lower voltages are increasing transistor count. The number of transistors for the same circuit has increased significantly just to do the same function.”

It also requires methodology changes. “Today, parasitics are in same order of magnitude as design parameters,” he notes. “In the past, designers were able to run most simulations pre-layout. Then toward the end of the design, they run extraction and do post-layout verification. Now, the parasitics are impacting how the design behaves because these parasitics are similar to other parameters in the design. Customers have been seeing a 30% difference in results between the pre-layout and post-layout. This means they need to start the design with post-layout simulation.”

Siemens’ Balasubramanian agrees. “For advanced nodes, post-layout sims are a must. Gone are the days where pre-layout sims were good enough. The effect of parasitics and device noise are now the critical factors affecting analog designs. In other cases, they also need to worry about aging requirements for SerDes applications.”

Conclusion
A new technology node may be optimized for digital, but if it cannot implement basic analog circuitry then it has no practical value. It does not need to have the greatest analog specification, just so long as it is good enough.

When this is coupled with new packaging technologies, there is a greater degree of freedom. “We expect that only a minimal of analog parts will be implemented in that technology, and a chiplet approach used for most of the analog part,” says Fraunhofer’s Heinig. “Then, only a PLL and chip-to-chip interfaces are necessary in the GAA technology.”

There is certainly a lot of research and development surrounding the creation of a good die-to-die communications that will not tax the analog circuitry too heavily.

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