New fan-out technology under development; 2.5D trouble spots come into focus.
Systems in package are heading for the mass market in applications that demand better performance and lower power. As they do, new options for cutting costs are being developed to broaden the appeal of this approach as an alternative to shrinking features.
Cost has been one of the big deterrents for widespread adoption of 2.5D. Initially, the almost universal complaint was that interposers were too expensive, which is why the majority of early adopters were in price-insensitive markets such as chips for servers and network switches. But there are less-obvious costs, as well. All of these packages need to be custom-designed because there is no standardized way of assembling various components into a package the way they might fit into an SoC. And not everything goes together seamlessly, adding to the time and overall cost and potentially affecting yield, which further drives up the price tag.
Cost isn’t the only stumbling block, though. As companies developing these chips are finding out, there are a number of less obvious technical problems, including everything from different coefficients of expansion to testing and simulation issues. This is why TSMC Integrated Fan-Out (InFO) packaging has caught on over the past year. Fan-outs are a much simpler approach to heterogeneous integration than 2.5D. Rather than designing multiple chips using an interposer or some kind of silicon bridge, they basically can be pushed closer together on a board and then packaged. But how close together isn’t always clear.
“The routes used to be 10 to 20 microns, so you could basically ignore the buzzing of the die at that geometry,” said John Ferguson, technical marketing engineer at Mentor Graphics. “Now they shoot for 5 microns, but ultimately it’s going down to 1 to 2 microns, which raises a question about how much interaction is going on with the different die.”
That interaction could become more prevalent with higher-density fan-outs, which basically are a middle-of-the-road advanced packaging approach between existing fan-outs and 2.5D in terms of power, performance and area.
“We used to look at the fan-out, which has a capability now of about a 2-micron line and space, as a poor man’s TSV or interposer,” said John Hunt, senior director of engineering at Advanced Semiconductor Engineering (ASE). “We came out with a high-density fan-out in January, which is a 16nm and 28nm die side-by-side fan-out, but instead of being a package with balls, it has bumps on it. It’s then treated as if it’s a die, and then placed on a BGA (ball grid array) substrate. It’s a hybrid solution. But using the fan-out eliminates the need to use a through-silicon vias interposer.”
Hunt noted that ASE currently has 12 variations of fan-out in various stages of engineering and development.
2.5D moves everything much closer together, leveraging high-bandwidth memory and high-speed interconnects. In doing that, it also adds some problems that need to be understood and thought through by chipmakers.
“Some materials expand more or less than others, and multiple layers expand or shrink at different rates,” said CT Kao, product engineering architect at Cadence. “If you deposit material on the wafer, you may see the wafer bulge up or down. The same is true of packages. If you have different materials in the package, a temperature change can cause big problems. If you have a mismatch it causes thermal stress. We’ve seen this in the polymer, which is organic, which is used to enclose the chip. It can shrink more than the metal.”
A second problem is warpage, which can occur when an organic material absorbs moisture from the environment. “We’ve seen a problem with the solder joints between the package and the PCB,” said Kao. “During manufacturing, the package and the PCB warp at different amounts. The corner balls experience more stress and the worst. That’s a function of ∆T and thermal expansion. There’s also residual stress, which depends on what temperature you put the package together. If you use a high temperature for reflow, it’s stress-free at the time, but as it cools down the stress increases.”
The worst-case scenario is a die crack inside the package due to different materials, which can lead to chip failure.
There are some familiar problems that need to be taken into account here, as well, such as parasitics. “As the package gets hot, the parasitics change,” said Mentor’s Ferguson. “Resistivity changes with temperature. As you put everything in a package, you can change the path of the heat sink. We need to understand the temperature impact on the die. We do know that dies at advanced process nodes are sensitive to stress. How that impacts the transistors themselves is unknown. There are a lot of questions on all of this. How accurate is accurate enough, and what are the appropriate use models?”
Answers to those questions are still not entirely clear.
“Thermo-mechanical stress is indeed a problem,” said Max Min, senior technical manager at Samsung. “ We have worked on TSV-based, and we have put this together with micro-bonding in the packaging. There is indeed a lot of mismatch between the thermal-mechanical coefficients when you have a lot of microbumps. How we put designs together may affect the underlying transistor structure and stress and mobility. We need to model them and design them with an understanding of the material side. That’s an issue.”
Creating blueprints and models
As more of these systems-in-package reach the market, there is more history to show what can go wrong and more data on how to fix problems or avoid them in the first place. This is a prerequisite for building economies of scale into the design through manufacturing process.
“The goal is to put more in less space,” said Bill Bottoms, chairman of Advanced Polymer Monitoring Technologies, a spinoff from Tulane University. “The problem is power. You can’t get things close enough together because of power density, so when you need high performance you have to keep the frequency low.”
One way to achieve that is through new architectures and packaging. A heterogeneous integration consortium—supported by IEEE’s Components, Packaging and Manufacturing Technology Society (CPMT), and sponsored by SEMI and the IEEE Electron Devices Society—is working on a series of blueprints to iron out best practices and processes for making that happen.
In addition, Si2 has a chip-package co-design group that is working to understand what is required for a design flow on advanced packaging. Mentor’s Ferguson pointed out there also is more attention being paid in conferences to advanced packaging. “A few years ago if you went to a packaging conference, it was equipment, engineering tools and testers. That’s starting to change.”
All of this will help add some structure to 2.5D packaging to enable volume production, after which Bottoms predicts the price will drop significantly, regardless of whether the interposer is organic, silicon or glass. “This is no longer just about the process node. You shouldn’t have to force memory processes on logic, and you cannot make RF on a logic process.”
It also will help add structure for 3D IC, which is still the least expensive approach to achieving throughput and density. Exactly where this packaging approach takes root, though, isn’t clear. While the focus has been on processors, memory has been stacked for some time, and some sensors are being packaged using this approach.
“If you look at image sensors, that satisfies all of these criteria,” said Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. “There are through-silicon vias. There are logic die in cameras that is below the sensor. And these are very, very thin die. It’s in very high-volume production and it’s also very cheap. 3D is happening in a very big way, but in a different area than we typically look at.”
He noted that for high-performance CMOS, 2.5D is current best approach. But it’s certainly not the only option. One of the big challenges is that packaging approaches are so tightly married to applications that it’s overwhelming to wade through all of the possible options, even for experienced engineering teams. Just coming up with the right parameters for models is difficult.
“Your model is only as good as the data that goes into it,” said Arkalgud. “And then you keep validating it over and over and you come up with something reasonable.”
Whether the tools are sufficient to deal with this is a matter of debate, too. The current thinking is that many of the existing tools work well enough for 2.5D. Whether they work for 3D is uncertain.
“If you look at 2.5D, it’s not that demanding,” said Mike Gianfagna, vice president of marketing at eSilicon. “We’ve been able to develop proprietary analysis tools for thermal stress and warpage. But for real 3D, that’s going to require massive retooling. You start moving parts of the system and the specs you have in place about which slice is where and how you’re going to manage thermal stress—that affects the whole design flow.”
Fine tuning this process will be challenging, as well. “We understand enough physics to understand what will be the likely problems,” said Mentor’s Ferguson. “The bigger challenge is prioritizing which impacts will be the most critical. So your design methodologies may be okay but if you have poor yield you have to scramble to fix it.”
The final piece is testing. There has been a lot of focus on how difficult it is to test 3D-ICs because there are no exposed contacts for attaching probes. But testing high-density fan-outs and 2.5D chips isn’t so simple, either.
“With 2.5D, you still have components integrated inside the package,” said Joey Tun, principal market development manager at National Instruments. “You’ve got integrated passive components. You also have functional density, which makes it significantly harder.”
The push into advanced packaging is inevitable as it becomes more difficult, expensive and time-consuming for most companies to continue shrinking features at the most advanced nodes. The end of the ITRS road map is a tacit recognition that change is required, and that change will come in many areas—materials, packaging, software, IP, tools, equipment and processes.
All of these areas will undergo significant change over the next few years as the semiconductor industry retools from a centralized compute architecture, whether that is a PC or a phone, to a more connected and distributed and increasingly diverse compute environment.
As William Chen, a fellow at ASE, observed rather succinctly, “We need to understand how things fit together.” That will take years, but it also will shift the focus of the semiconductor industry well beyond just the chip to the package, the system, and possibly even well beyond that.
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