Are Models Holding Back New Methodologies

Experts at the Table, part 1: ESL methodologies are not coming together for many companies, but there is hope on the horizon.


Semiconductor Engineering sat down to discuss the state of the industry for modeling at abstractions above RTL, a factor which has delayed adoption of Virtual Prototype and the proliferation of system-level design and hardware/software codesign. Taking part in the discussion were Frank Schirmeister, group director, product marketing for System Development Suite at Cadence; Bill Neifert, CTO for Carbon Design Systems; Nick Gatherer, engineering manager for models within the processor division of ARM; Victoria Mitchell, director for SoC software within Altera; Marleen Boonen, CEO and founder of Methods2Business; and Tom De Schutter, product marketing for Virtualizer at Synopsys. What follows are excerpts of that conversation.

Modeling panel

SE: What is the current state of the industry when it comes to modeling for virtual prototypes?

Neifert: People are certainly using virtual prototypes. They have emerged from the labs and research projects to a mainstream part of the flow. In large part it is because of the number of models that exist now. In Europe, the large companies tend to have internal modeling efforts, but in Asia and the U.S., they are adopting the models provided by the Intellectual Property providers. The IP providers have settled on a strategy of providing fast functional models, and for accuracy, many of them are partnering with us. The area in the middle is very under-represented. I do not see the connection much between High Level Synthesis and the virtual prototype. This is necessary to deliver on the promise of ESL. In practice companies are adopting one or the other and rarely both.

Boonen: Methods2Business is an IP design center and we are SystemC-based. When you have complex IP cores, such as WiFi, where there is a complex combination of hardware and software, the only way to build that is to go with SystemC. This enables you to have your software and hardware together from the very beginning. That SystemC model becomes a common reference for the design. All the verification and validation is based on that SystemC model. This is also our model for high-level synthesis and in the virtual platform. I believe that HLS, SystemC and ESL is becoming a fact now because we are no longer talking about models which are nice to have and the models are becoming the design models. This was the last piece that was missing when you are trying to promote virtual platforms. It is now your design model and the validation model for software and the basis for multi-language Testbench and Verification. For IP design and next generation IP it is unavoidable to have SystemC. At RTL there is no way to get my software up and running.

Mitchell: My team at Altera is responsible for software engineering and system modeling, and we clearly understand the advantages of a virtual prototype as an enabler for early software. It is a significant investment to assemble the virtual prototype, to do early software enablement, so we need to find other ways to capitalize on that investment through other functions, either downstream or upstream, Most recently we have started to investigate the early prototyping before there is a single line of RTL created to see if we can do verification with that. The use of a golden model is important as way to drive the rest of the design flow. But I don’t think we are there yet as an industry. There are point solutions but we need to see wider adoption so that we can drive more use-cases.

Gatherer: From an IP supplier’s point of view, the killer apps for virtual prototyping is the idea of getting the software development happening concurrently with the hardware. This is not just to collapse the time to market, but also to get the benefit of developing those two parts concurrently so that you can optimize the design rather than just having to cover up problems with the software because it is too late to change the hardware. Not all of the issues we have to face are technical. Some are organizational. For example, staff may be unavailable because they are still working on the previous generation. A lot of the technology we need has been there for quite some time. There are things that have enabled significant usage of virtual platforms for software development. IP providers have taken a role to make sure models are available and the investment in the models has being made. They are available at the right time and right quality to give companies the confidence to use this methodology. Because of this, customers are making significant inroads into getting products to market faster. The time from silicon to full system up and running is not measured in months anymore, which it used to be, but in days. These are complex SoCs with full software stacks. Providing the models and making sure the quality is there is a key part of this.

De Schutter: The usage of models for a virtual prototype is migrating from being a low-level software task up to higher tasks, such as Linux porting. The next step is to do the driver development for the IP models that you are making available, having virtual prototypes available for all interface IP and make sure that the driver development can start on top of that. Then we can look at it from an SoC point of view. We don’t have all of the models yet because much of it is semi-specific IP. Some companies have embraced having a modeling team and embracing this methodology but in others it is not a fully rolled out methodology. At companies, such as Altera, we have seen a lot of investment into creating these models and having a virtual prototyping strategy, but it is not across the whole industry yet. It is still somewhat mixed. We are seeing more adoption and people are beginning to speak about the value of virtual prototypes.

Schirmeister: I have been an ESL enthusiast for the past 15 years. I take a slightly contrary view in that modeling is a hindrance for the adoption of virtual prototypes. There are areas in the SoC where we are there, namely the interconnect. Interconnect guys, such as ARM, Sonics and Arteris, have figured out how to get a high-level description, to parameterize their IP, and generate everything automatically from that. This works. High-level synthesis for IP blocks is getting there. We still have a ways to go. The challenge is that the next level of description only works for high-level synthesis and not really there for virtual prototyping. For IP reuse, we are not quite there. It is there for the high profile IP, but not for some of the lower-level IP yet. The worst part – the only golden model is the integrated RTL. The topology of how things connect together is not there. There is no automation to go from there down to the silicon virtual prototype. The main issue is modeling. Today, users switch (between RTL and virtual prototype) based on the availability of models. If I don’t have a fast model, I might take the RTL and Carbonize it – that helps me a little bit, they take what they have and do not insist on a full coherent model at the next level.

In part two, the panelists will discuss what is changing and what needs to happen to get more of these ESL methodologies working.