Etched copper lines are showing huge promise using new process technology.
Electromigration and resistivity present serious obstacles to interconnect scaling, as previously discussed. In a copper damascene process, grain growth is constrained by the narrow trenches into which copper is deposited. As the grain size approaches the mean free path of electrons in copper, electron scattering at sidewalls and grain boundaries increases and resistivity jumps. Meanwhile, increasing current density increases the driving force for electromigration, even as smaller grains increase the number of void nucleation sites.
Most approaches to the problem have considered thinner barrier layers and ways to improve copper adhesion. Instead, researchers at Tokyo Electron and IMEC stepped back and examined the fundamental premise, that copper interconnect schemes must use an inlaid damascene integration process.
It is worth remembering that aluminum interconnects were manufactured by a subtractive process—deposit a blanket aluminum film, etch trenches in it, then fill those trenches with dielectric. Use CMP to planarize the structure if needed. The introduction of copper brought a shift to inlaid metal because copper is very difficult to etch, with non-passivating, non-volatile etch by-products.
However, that was in 1997, when the industry was just coming to grips with the 0.25 micron (250 nm) technology node. Metal 1 copper lines in Intel’s quarter-micron logic process were 480 nm thick. Now, as manufacturer consider their options for sub-10 nm technology nodes, line thickness for critical layers is dropping into the 50-nm range. Thinner layers mean less material to remove, and potentially a less challenging etch process.
In work presented at this year’s IEEE Interconnect Technology Conference, while the researchers did not disclose the details of their etch and clean processes, they reported only a thin layer of CuO remaining on the copper surface. The copper lines, 44nm wide at the mid-point, were somewhat rounded, with a 74.5 degree sidewall in the top half of the line and near-vertical sidewalls at the base of the line.
Perhaps more important, preliminary electromigration and resistivity results were quite encouraging. Grain size was between 10^3 and 10^4 nm, even before any efforts to optimize it. According to Zsolt Tőkei, IMEC’s program director for nano interconnects, resistivity in particular was 15% better than achieved in comparable damascene structures. Unlike other proposals to address copper’s resistivity and electromigration problems, etched copper lines introduce no new materials into the interconnect stack.
Certainly more work remains to be done. Isolated lines are not a complete process flow. In particular, Tőkei warned, copper films are opaque, and will require new alignment methods. Landing damascene vias on etched copper lines may prove particularly challenging. Still, Tokei did not see any obstacles that would prevent incorporation of etched copper lines for the N5 technology node.
If that is true, the implications are profound for both the dielectric and metal components of the interconnect stack. The requirement that the dielectric survive the damascene process — etching, barrier layer and copper deposition, and then copper CMP — has significantly limited candidate dielectrics. Many otherwise promising materials simply cannot maintain their properties under these conditions. Depositing the dielectric after copper deposition and patterning would reduce or eliminate damage and simplify the integration of lower dielectric constant materials and even air gaps. (Indeed, Tőkei observed that the normal IMEC passivation flow resulted in the formation of air gaps between the copper lines.) The ability to use lower dielectric constant materials should more than offset the relatively high dielectric constant of the SiN sidewall barrier.
Much more work remains, but etched copper lines could prove to be the biggest change to the interconnect stack since, well, copper itself.