EDA companies, OSATs, and foundries must collaborate to ensure wafer-level packaging yield and performance.
Wafer-level packaging enables higher form factor and improved performance compared to traditional SoC designs. However, to ensure an acceptable yield and performance, EDA companies, OSAT companies, and foundries must collaborate to establish consistent and unified automated WLP design and physical verification flows, while introducing minimum disruption to already-existing package design flows.
Wafer-level packaging (WLP) is a promising “More than Moore” technology that enables higher form factor and improved performance compared to traditional system-on-chip (SoC) designs. Unlike 2.5D and 3D integrated circuit (IC) designs, WLP doesn’t require through- silicon vias (TSVs), which are expensive, and may cause mechanical and thermal reliability issues. There are two WLP styles predominantly in use:
Both styles enable single-die and multi-die integration. However, for the multi-die fan-in process, multiple dies are typically from the same silicon wafer (homogenous integration). In the case of fan-out wafer-level packaging (FOWLP), the die integration can be either homogenous or heterogeneous. The example of FOWLP design shown in Figure 1 utilizes the package-level redistribution layers (RDLs) to connect from the die to external ball grid arrays (BGAs), and between die in multi-die configurations.
Figure 1: Fan-out wafer-level packaging
Currently, major outsourced assembly and test (OSAT) companies and foundries offer different flavors of FOWLP technologies. STATs ChipPAC’s embedded wafer-level ball grid array (eWLB) technology is a space-efficient package design enabling a smaller footprint; higher density I/O, and lower package profiles than is possible with laminate or flip chip semiconductor packages. Amkor’s silicon wafer integrated fan-out technology (SWIFT) incorporates some unique features not associated with conventional IC packages, such as the inclusion of polymer-based dielectrics, multi-die and large die capability, interconnect density down to 2 μm line/space (critical for SoC partitioning applications), copper pillar die interconnect down to 30 μm pitch and the use of through-mold vias (TMVs) or tall Cu pillars. TSMC’s integrated fan-out (InFO) wafer-level packaging is a silicon-validated technology that comes in different package sizes: 8x8mm2 (which allows mono-die or multi-die, and supports up to 600 I/O count), 15x15mm2 (allowing up to 2000 I/O count), and 25x25mm2 (allowing up to 3600 I/O count).
FOWLP design and verification
Design and verification flows for SoCs are well-established, and have been used by designers for decades now. For a certain process node, the foundry typically provides a set of design rules that SoC designers must strictly follow to ensure correct manufacturing of the SoC by the foundry. Electronic design automation (EDA) companies develop an automated physical verification flow to help designers analyze an SoC design using software tools that are fed by the foundry rules in a specific format. These tools display any design rule violations found, and can even correct many errors automatically. The same automated verification flow is developed for connectivity checking, parasitic extraction, post-layout simulation, etc. As a node matures, the foundry eventually supplies designers with a fully-developed SoC process design kit (PDK) for the process node that the designers use, in conjunction with a set of EDA tools and processes (reference flow) supplied by the EDA vendor, to deliver a design that is compliant with the foundry design requirements and manufacturing process.
From an IC packaging perspective, package design and verification flows are much simpler than those used for SoCs. In fact, many package designs are assembled manually. They typically have very little in the form of formal sign-off requirements that accompany the package design, other than a textual document describing the intended design rules. Consequently, the EDA tool functionality for package design and verification has historically been much simpler as well.
However, for packaging technologies such as FOWLP, the package design and verification process has suddenly become much more complicated. Because FOWLP manufacturing occurs at the “wafer level,” it incorporates mask generation, similar to the SoC manufacturing flow. That means solid package design and verification flows must be in place so the designer can ensure manufacturability of the FOWLP by the foundry or OSAT company. Similar to the PDKs used for an SoC, the foundry or OSAT must now provide the package designer with some form of an assembly design kit (ADK), as shown in Figure 2.
Figure 2: Package assembly design kit components
FOWLP challenges in package design environments
When establishing a design and verification flow for FOWLP, one of the main challenges is bringing together the chip and package design environments. To verify the manufacturability of the FOWLP mask, the package design must usually be exported to GDSII format from the native design enviroment. However, package design tools typically only export to other board-level formats, such as Gerber. GDSII export capabilities have only recently been added. One of the issues that frequently occurs is when the GDSII file that represents the package design includes some “illegal” shapes that can’t be interpreted correctly by the physical verification tools, because these shapes don’t conform to the typical GDSII format. An example of such shapes is shown in Figure 3. This non-orientable shape (meaning the exterior and interior of the shape along a certain edge are ambiguous) cannot be interpreted correctly by GDSII standards.
Figure 3: Non-orientable shape in GDSII
In this case, the designer has two options: edit the shape to conform to GDSII requirements and repeat the GDSII export process from the design environment, or keep the non-orientable shapes as is and ignore them on input to the physical verification tools. The first option adds time to the schedule, while the second option may cause real violations to be missed, which can cause a yield issue after manufacturing. Eventually, for better support of FOWLP design and verification flows, package design environments will need to be enhanced to allow proper export to mask-level formats such as GDSII.
Using SoC physical verification for FOWLP
Once a proper GDSII file representing the package design is available, well-established, IC-driven verification tools can be used to perform the required checking on the FOWLP design. These tools enable an automated verification flow similar to SoC verification. Using GDSII-based physical verification tools for FOWLP designs has numerous advantages:
That said, using GDSII-based physical verification tools for FOWLP presents some challenges. From a rule checking perspective, coding the manufacturing rules must be done carefully to avoid highlighting false rule check violations. For example the existence of non-Manhattan shapes in a FOWLP design can generate false errors. From a connectivity checking perspective, most IC-driven connectivity verification tools rely on identifying transistor shapes in the layout, so they can correlate the source netlist with the layout netlist for connectivity checking. When this checking is mapped to the packaging world, a FOWLP design doesn’t contain any transistors or active devices. Adding to the challenge is the netlist format, which is usually SPICE or Verilog for IC-driven design, but typically a spreadsheet or AIF format in the case of package-driven design. And from a usability perspective, most SoC verification tools operate on LINUX systems, while package design enviroments typically run on MS Windows systems.
Uniting ICs and packages
To overcome these challenges, some EDA vendors have developed new EDA functionality to bridge the gap between the IC world and the packaging world, while introducing minimum disruption to the already-existing package design flows. For example, the Calibre platform from Mentor Graphics contains a number of verification tools that can be used to verify FOWLP designs:
The Calibre 3DSTACK functionality extends die-level signoff verification to enable designers to perform signoff DRC and LVS checking of complete multi-die systems at any process node without breaking current tool flows or requiring new data formats (Figure 4). It uniquely identifies geometries per layer per die placement in the assembly, allowing accurate checking between dies. With the ability to differentiate the layers of interest per individual die placement, the Calibre 3DSTACK tool enables designers to verify the physical attributes (offset, scaling, rotation etc.) of each die, while also tracing the connectivity of the interposer or die-to-die interfaces.
Figure 4: Calibre 3DSTACK functionality
With this kind of connectivity between ICs and a package, package designers can use a package source netlist exported from the package design environment in a spreadsheet or AIF format to check that all the die in the FOWLP are connected correctly through the RDL layers of the package, and to check each die’s connections to the external I/O (usually BGA). Most package design environments can export an AIF netlist— a multi-chip module (MCM) file that contains the location information of the package bumps and the BGAs in x,y coordinates form. Sometimes package design environments export a spreadsheet (.csv file) instead of the MCM AIF file. However, the AIF file is advantageous in the sense that its format allows the description of the bump/BGA shape (square, octagon, circle, etc.), while the spreadsheet includes only the center point (x,y) locations of the shape). The foundry or OSAT provides a connectivity stack of the RDL layers for the FOWLP that can be considered “golden” by the package designer. This checking is similar to layout vs. schematic (LVS) checking in the SoC verification flow.
Its many advantages position the FOWLP design as one of the keys to the future of “More than Moore.” However, for FOWLP designers to ensure an acceptable yield and performance, EDA companies, OSATs, and foundries must collaborate to establish consistent, unified, automated design and physical verification flows. Because FOWLP manufacturing requires mask generation, SoC physical verification tools are the best logical fit. Uniting package design environments with SoC physical verification tools ensures the necessary co-design and verification platforms are in place.