There’s no such thing as a simple cost decision with EUV at its current power level.
Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process.
Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process optimization and yield learning improve system uptime and die yield. Equipment sets become more reliable and cost less to run. Over time, the wafer cost comes down. The transition actually takes place when transistors made with the new process are less expensive than the older technology. As manufacturing becomes more complex, achieving the cost savings promised by each new technology node is becoming more difficult, and the cost risk is one reason why companies delay technology transitions.
The lithography process carries much of the economic burden associated with technology transitions. As previously discussed, the 10nm and 7nm nodes are forcing manufacturers to decide between two unpleasant alternatives. The incumbent technology, 193nm immersion lithography, simply cannot print the feature sizes required without complex and expensive multi-patterning schemes. Numerous layers will require triple or even quadruple patterning at these nodes. Some exposure options will severely constrain designers, forcing increases in cell area. But the long-awaited alternative, extreme ultraviolet lithography, has yet to demonstrate the reliability or throughput expected of high volume lithography systems. Thus manufacturers must decide which option will be the most cost-effective, and when to introduce EUV into their fabs.
For the last several years, Mallik and co-workers at IMEC have been refining a lithography and process cost model to address these questions. While they caution that their model makes many assumptions which may affect the results, they conclude that EUV will offer a cost-effective alternative for some process levels by the N7 node, even with very conservative throughput estimates.
The critical layers used in their analysis are detailed in Table 1. As the table shows, many of these will require at least triple patterning at N7 if 193nm lithography is used. For this reason, at an EUV throughput of 150 wph, the choice is easy: EUV offers a clear cost advantage of as much as 30%, depending on the layer. There’s only one problem: EUV systems can’t expose 150 wph yet. Given photoresist sensitivity of 15mJ/cm², a 250 W exposure source (measured at the system’s intermediate focus) would expose only 126 wph, and an 80 W source only 50 wph. So far, 80 W is about the maximum achievable source power; 150 wph throughput is probably a long way off.
In the meantime, though, it turns out that a more achievable throughput still offers significant benefits for some process levels. In Metal1 and Via0, EUV is cost-competitive with 193nm immersion at a throughput as low as 50 to 60 wph. Reducing the number of masks, simplifying overlay between exposures, and allowing designers to use area-minimizing two-dimensional structures offsets the greater cost of EUV itself. Indeed, the IMEC group concludes that the BEOL stack is an ideal candidate for early EUV introduction.
In local interconnects, the situation is different. Local interconnects are the most aggressively scaled part of the design; even EUV exposures are likely to benefit from the use of a 193nm cut mask exposure. To achieve comparable cost to 193nm exposures, EUV would need to achieve 70-90 wph throughput. Similarly for gate patterning, where the break even point for EUV is about 85 wph. The increase in lithography cost with EUV is offset by the reduced number of etch steps, but the use of FinFET devices already limits the number of design options.
The benefits of EUV for any particular fab’s process will depend on the exact lithography approach that is chosen. For example, a fab might only use EUV to replace the complex multi-patterned block/cut layers in the BEOL stack, which would reduce lithography costs but would not ease the need for uni-directional metal designs. Or, it might introduce a full EUV-patterned metal stack, allowing the use of bi-directional metal designs and thereby reducing the chip area. Both of these approaches are potentially less expensive than a 193-nm only approach at N7, on both a die and wafer base. Again, however, the exact cost savings are dependent on EUV throughput.
Arindam Mallik, et. al., “The need for EUV lithography at advanced technology for sustainable wafer cost,” Proc. SPIE 8679, Extreme Ultraviolet (EUV) Lithography IV, 86792Y (April 8, 2013);
Arindam Mallik, et. al., “The economic impact of EUV lithography on critical process modules,” Proc. SPIE 9048, Extreme Ultraviolet (EUV) Lithography V, 90481R (17 April 2014);
Arindam Mallik, et. al., “Maintaining Moore’s law: enabling cost-friendly dimensional scaling,” Proc. SPIE 9422, Extreme Ultraviolet (EUV) Lithography VI, 94221N.