IBM, GlobalFoundries and Samsung have made a breakthrough.
A consortium of companies involving IBM, GlobalFoundries and Samsung has rolled out the first 7nm test chip using silicon germanium as a substrate, using EUV to pattern multiple layers.
While this doesn’t mean the cost equation is even close to being solved, or that more than a handful of companies will push forward to that node anytime soon using SiGe as the substrate material, it does create one more technically possible option for chipmakers. Perhaps more important, it shows that EUV is at least functional, even if it isn’t perfect or quick enough. Most companies have been expecting EUV to replace 193nm immersion since 45nm. The fact that it is useful at all is cause for celebration. Whether it will roll back to 10nm and even 14/16nm remains to be seen, but at least now there is concrete evidence of progress.
At 7nm, even EUV will require double patterning. But compare that to octa-patterning using 193nm immersion lithography and the attractiveness of this technology becomes obvious. Most companies working at advanced nodes are comfortable with double patterning with colors at this point. Using EUV at 7nm will be a rather straightforward transition if the cost is reasonable. That cost will be measured in terms of the up-front equipment, demand, and the time it takes to process a wafer.
There are still other options for making this work. Directed self-assembly has been under development by the same group of companies, and presumably would be used for at least some of the metal layers. There also is work underway involving selective deposition.
From a materials standpoint, SiGe has been in use for some time, and has been the leading candidate for 7nm and 5nm chips. Whether it will stay in the lead, or whether it will need to be replaced by Ge or III-V materials at the most advanced nodes to enable electrons to pass through materials more easily, is at this point unknown. Quantum effects will become much more prominent at 7nm, impacting performance, power, and the entire design flow. The movement of electrons is not consistent at those geometries, meaning they enter and leave devices such as memory at unpredictable rates.
Still, being able to develop 7nm chips in a lab—in this case, at SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering—is a big step forward for improving performance through higher density, lowering power (although dynamic power management will be a growing problem), and certainly opening up more real estate on a die.
It’s also possible that 7nm die will be used as the logic platform for 2.5D and 3D-ICs, so memory can be positioned closer to the processing elements using wider interconnects to reduce resistance. One of the advantages of stacked die is that the individual dies within that stack can be developed at any process node, so analog sensors can be developed at 55nm and memory can be on the same die or on a different die.
The view from 60,000 feet, though, is that Moore’s Law is rolling again, even if it requires a few corollaries to the definition. Foundries are fully functional at 16/14nm, and they are working on 10nm as the next logical step. 7nm now looks possible, which means much more activity in the near future from EDA and IP vendors, from foundries looking to develop processes and improve yield, and from equipment makers to improve the number of wafers moving through per hour with fewer defects. This is a vast operation with many incredibly complicated working parts, and it appears they’re all about to start moving again. Break open the champagne.