Inside Lithography And Masks

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at Imec; Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries; David Fried, chief technology officer at Coventor; Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); and , chief executive of D2S. What follows are excerpts of that conversation.

SE: What are some of the big challenges from your vantage point?

Fried: At the highest level, what I’m concerned about is the volume driver for any of these technologies. For most of our lives, we knew we were going to do the next technology. We knew why. Then you built it and you had customers. Right now, most people can’t see too far past 7nm, which is what we are all working on. Nobody really knows what is going to fill the fab at 7nm. There are a handful of customers that are going to get there. I don’t know that anybody sees the driver, or the volume driver specifically, at any node beyond that. At the same time, we are talking about EUV insertion. Maybe we get it in a little bit at 7nm, so that we learn about it. So then, we are ready to go for 5nm. But what’s there? What is the promised land on the other side of this insertion? Plus, how many customers are there going to be at 7nm? It’s going to be a significantly smaller number beyond that. A lot of that has nothing to do with our part of the industry. The design costs to get into these technologies are really what’s starting to be the killer. I firmly believe we can put a cost-effective 5nm scaled technology out there. It would be expensive and it would get some scaling. But the design cost to get into these technologies is now starting to become the customer killer or the product killer. We are no longer in that scheme of ‘if you build it the customer will come.’

Levinson: I have a couple areas of focus. One is trying to finally get EUV lithography into high-volume manufacturing. As an industry, we are going to do it. But it’s going to be painful. And it’s often just the mundane things. For example, there’s equipment reliability. When you are in manufacturing and your tool is down a lot, that’s a very painful place to be. Regarding 5nm and beyond, there are issues at the device level. There are problems with the interconnects. I can make contacts that are so small, and you can fill it with the best metal available. They are still too resistive for anybody to use. I can make some of them, but it’s hard to reproduce them. We are also now getting to the point where the variability levels are the size of molecules. This is not just the polymers, but also the monomers that make up our resists. We are getting to a point where there are major issues on every front to go to the next node. It will be a challenge for the industry at 5nm and beyond.

McIntyre: From a litho/EUV perspective, one of the challenges will be to not get complacent and assume EUV is a done deal. One of the more exciting things about this year compared to last year is that the plan really hasn’t changed. We are still on the same trajectory for the insertion of EUV in the 2018 time period, sort of late into 10nm/7nm, and certainly the workhorse for N5. But by far, it’s not a done deal yet. We’ve come a long way, but there’s a lot of room left to go, ensuring we can get the variability down to an acceptable level. We need to ensure our tools are performing and stable month after month, not just day-to-day. We must also ensure that the whole infrastructure, which has made a lot of progress over the last year or two, continues to make that progress so EUV is ready on time.

Fujimura: Any time there is discontinuity in the market, it’s both an opportunity and a threat. We have to think about our own businesses and how we can turn this into an opportunity. So, I see EUV is something that’s now worth investing in, particularly for the mask infrastructure. The mask infrastructure has to get ready before the industry can do reasonable wafer characterization. They have to get ready by 2018. That’s next year. So it’s imminent.

SE: Let’s start with extreme ultraviolet (EUV) lithography, and then move to the other lithographic technologies. EUV is not in mass production yet, but it is making progress. ASML is readying its latest EUV scanner—the NXE:3400B. Initially, the tool will ship with a 140-watt source, enabling a throughput of 100 wafers an hour. A 210-watt source is in development. Where are we in EUV and what’s missing?

McIntyre: There are multiple tools out there that are fairly stable, operating at the 125ish-watt range. There are demonstrations above 200 watts. There seems to be a pretty good path in terms of getting to something above 200 watts by the time it gets inserted in HVM. So from that perspective, things are moving in the right direction as planned in respect to the tools. For the rest of the infrastructure, the mask making readiness is there, at least from an initial development cycle perspective. But can it produce the number of blanks or the number of masks for production quality and quantities that will be needed? That still has to be ironed out. The pellicle is one of the key remaining issues. So there is progress with pellicles, but it’s not clear that we have an HVM solution yet to get up to 250 watts or so. That’s one area we are working on.

Fig. 1. Pellicle prototype. Source: ASML

Hayashi: On the mask side, we need to obtain inspection capabilities. It’s quite difficult to detect all defects. If we can’t detect them, they may end up getting printed on the wafer. We need an actinic EUV source inspection system, especially with a pellicle. That’s a very difficult issue, because we need a large investment to develop or realize an actinic system. Still nobody wants to do it. Maybe it will take another four or five years to develop it. In addition, there is the pellicle. There is progress in the materials screening process. We still have at least three groups of pellicle material types—polysilicon, silicon nitride, and carbon nanotubes. We need another year to narrow the candidates. After that, we need to realize a pellicle material for commercialization with a target for production. It may take another two or three years. We still have a long way to go for this kind of infrastructure.

Fujimura: EUV also needs multi-beam mask writing. Fortunately, multi-beam mask writing is ready. That is a great opportunity to take advantage of the things we couldn’t do before. It is needed, particularly for EUV. In EUV, you don’t have double patterning yet. But you still have to scale the number of features that you want to write. You have additional problems on EUV masks. And in any case, multi-beam is going to end up being a necessary part of the mask infrastructure for EUV production.

SE: EUV tool availability is also an issue. On average, the availability or uptime for the current EUV tools in the field is somewhere around 75% or so, although the percentage continues to improve. I assume that is an issue, right?

Levinson: If you are going to do manufacturing, you have to be able to do things in a predictable fashion, so you can go to your customer and say: ‘I will have this many parts ready for you on this date.’ And if your equipment isn’t reliable, then you can’t inform customers in a predictable way and make good on your promise. It’s pretty painful when you go to the customer and say, ‘I know I promised you something, but it’s just not going to happen.’

SE: So what are some of the considerations in putting EUV into production?

Levinson: What people will do, of course, is buy enough tools to have redundancy and to get by. But that’s a very expensive proposition. For EUV to be a good and honest, cost-effective solution, we have to get past that. When is that going to be? It’s more than a year away.

SE: When does EUV get inserted and where? And what about the cost-of-ownership?

Fried: I take a pragmatic technology definition approach to where EUV comes in. I agree with the overall assumption that 7nm is the insertion point. But 7nm is the insertion point as an optical replacement. You do not define 7nm based on the capabilities of EUV. You define 7nm for optical with multi-patterning. Where you can insert EUV, you knock out multi-patterning modules. So, you don’t actually take advantage of EUV for anything other than a process cost savings. That involves a number of mask levels and a number of processes. Hopefully, you get a defectivity improvement by knocking out multi-patterning modules. But you haven’t taken advantage of the patterning capabilities of EUV when you do that. So where does it come in? It comes in at cut levels, block levels and via levels. If you think about the fin and cut, you are doing one level of SAQP for the fin and three levels of cuts. If you can take those cuts out with EUV, that’s great with single patterning. In the backend, it’s a level of SAQP plus three or four blocks. You can knock those out. Vias are triple or even quad patterning at the next node. And that’s where it will be inserted, but it won’t be a technology defining insertion. It will be a cost savings insertion. Hopefully, you can then start betting the farm at the next node and define the next node based on the capabilities of EUV. So, we are going to get an initial cost savings or process cost savings benefit when it gets put in first, and then hopefully, an area scaling benefit in the next version.

Fujimura: The thesis is that it would it be cost-effective to use EUV. The industry knows that the investment in EUV is for the future. And even if doesn’t happen at the next node, it has to happen at the next node after that, and so on. So it’s worth investing in it and allowing some of the money to flow to the people who are making it happen for the next node, even if it’s not cost-effective exactly. It seems like the industry is trying to make it happen, even if, for this node, it is not cost-effective, because it is a needed investment.

McIntyre: I agree with one assertion—inserting 7nm with EUV as is, in effect, is more or less a cost savings. Certainly, the next stage could be to really define a node so it takes advantage of EUV. But you could also see that even at the 7nm node dimensions, if we do a little bit of a swizzle on things at those dimensions by inserting EUV, it gives you a cost savings. It gives a potential electrical performance advantage by reducing capacitance and improving the overall power.

Levinson: Just to comment on the cost, we traditionally calculate cost by how much it costs to make a wafer. Then you decide how much, therefore, the die cost is, which factors in your yield. But there is another element, and that’s cycle time. It only takes five or six layers for me to replace multi-pattering with EUV. And I can knock off 20 masking steps, plus depositions, etches and so forth. If you think it’s 1.5 days between masking steps in multiple patterning, I save a month on my cycle time using EUV.

Fried: That’s as long as the tools are up.

Levinson: Again, it comes back to predictability. But if we can do that, that’s the other factor. Even though one could say it doesn’t quite make economic sense in the way we look at it traditionally, that consideration—cycle time—may just push it over the top.

Fried: But if EUV is not cost effective, it’s not going into the node. I don’t think anybody is sticking EUV into 7nm for the betterment of the community. It had better save some money or it’s not going to be there.

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