Inside Samsung’s Foundry Biz

Two top executives look at finFETs, FD-SOI, and when mass production will begin for 10nm.

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Semiconductor Engineering sat down to talk about the foundry business, process technology, design and other topics with Hong Hao, senior vice president of the foundry business at Samsung Semiconductor; and Kelvin Low, senior director of foundry marketing at Samsung Semiconductor. What follows are excerpts of that discussion.

SE: The foundry business has always been challenging, and the leading edge is becoming more difficult at each node. What’s changed in the foundry business in recent times?

Hao: The last couple of years have been significant for the foundry business. It’s been transformative. More importantly, we have brought competition back into the foundry business.

SE: You are referring to Samsung’s recent move to bring its 14nm finFET technology into production? Until then, Intel was the only company making finFET-based chips. Is that the case?

Hao: Over the past couple of years, there has been a lot of doubt about whether Samsung was able to deliver this. Now, we are actually in business with the 14nm node. We are in mass production with 14nm finFETs. Products built with 14nm finFETs are already in the market.

Low: We are also seeing a change in the market. The finFET race is very intense. What is apparent is there is now a true choice for customers of finFET technology.

SE: In recent conference calls, Samsung’s executives have stated that 30% of the company’s overall 300mm capacity is targeted for 14nm finFET production. Meanwhile, analysts from Pacific Crest Securities have indicated that Samsung will ramp its 14nm finFET capacity from 15,000 to 20,000 wafers per month today to 50,000 wafers per month by year’s end. Where is Samsung ramping up its 14nm finFET process?

Hao: In terms of production, 14nm just started a few months ago. We have two fabs in full production now. There is our S1 fab in Korea and the S2 fab in Austin, Texas. Also, our S3 fab in Korea is being prepared. In addition, we’ve licensed our 14nm technology to GlobalFoundries, which provides additional sourcing flexibility for customers.

SE: The 28nm planar node is expected to be a long-running node. Yet, the 20nm planar node will have a short life. What about 14nm? Will 14nm be a long-running node or not?

Hao: 14nm should be a very long node.

SE: Where is the industry in terms of the overall 14nm finFET ramp?

Low: 14nm is still in the early stages of customer acquisition. There are many customers with design activities out there. But we’ve definitely seen a pick-up from our lead customers. We are talking about design activity, products and tapeouts.

SE: What are the challenges with 14nm finFETs?

Hao: There are more complexities involved, such as multi-patterning. Over time, that will not be an issue. The tools will mature.

Low: For designers, multiple patterning is challenging. For 14nm, we are doing double patterning. For double patterning, we have two masks. You have color A and color B. Designers need to understand how to do designs with two colors now, which they have never experienced in the past.

SE: What else?

Low: For designers, it’s a learning process. Designers have been very familiar with planar technology architectures for many generations. However, finFET is a 3D device. Now, the channel where the current flows is 3D. We had to make it 3D so that the amount of current flowing in the area increases. If you do a cross section, you can see physical individual fins. You need to learn how to design with discrete quantized devices. It’s something new. The EDA community has helped because they are making the design process as transparent as possible.

SE: In its product portfolio, Samsung also has various 28nm bulk processes. You also have 28nm fully depleted silicon-on-insulator (FD-SOI) technology. Where does FD-SOI fit in?

Low: The value of ultra-low voltage finFETs is due to its fully depleted device architecture. FinFET is one way to do it. The other way of doing fully depleted is FD-SOI. This is not 3D-based finFETs. FD-SOI consists of planar transistors that have very low-power attributes for Internet of Things-type applications. Aside from that, the additional advantage of FD-SOI is body biasing. So if you use body biasing in your design, you can capitalize on the full potential of the wide-ranging power/performance attributes of FD-SOI.

SE: So which do you choose?

Low: There is a split between finFET and FD-SOI applications. FD-SOI tends to be more on the mainstream nodes. The goal is to avoid double patterning to keep the costs manageable. And yet, it still provides enough performance, as well as reduced power benefits.

SE: Does 28nm FD-SOI compete against 14nm finFETs?

Low: No. It complements 14nm. They have different densities. Both have different cost points. 14nm finFETs were created for more performance, lower power and more scaling. There is no doubt that 14nm finFETs will allow you to have a higher performance point compared to 28nm FD-SOI. In terms of power, finFET also provides the benefit of low power. However, if you look at overall costs, 28nm FD-SOI has a lower cost point than 14nm finFET. Depending on the end markets, many decisions are made around cost.

SE: Getting back to the leading edge, Samsung also is developing 10nm finFET technology. What does that bring to the party? And how far along is Samsung at 10nm?

Hao: 10nm has significant power, area and performance advantages. Today, we already have a silicon-verified PDK that’s been released to enable design flow development. Mass production for the 10nm node is expected by the end of 2016.

SE: How far along are you?

Hao: We have MPW (multi-project wafer) shuttles going already. We already have internal test chips. We have some early engagements with customers.

SE: But how many foundry customers can afford to do a 10nm design? Are there enough customers out there?

Low: Enough to get our attention. There is enough interest in the market.

SE: But aren’t there fewer foundry customers moving to the leading edge?

Low: There are more and more mergers taking place. The customer base is shrinking. The affordability becomes challenging for customers.

SE: The industry is ramping up 16nm/14nm finFET technology today, with 10nm slated for the end of 2016 or sometime in 2017. How will 14nm and 10nm play out in the long term?

Hao: They will co-exist for a long time to come.

SE: How different are your 14nm and 10nm finFET technologies? And can you comment on your 10nm technology?

Hao: I can’t comment on that right now. All I can say is that we will continue to have multi-patterning.

SE: What happens beyond double patterning?

Low: As you go into triple or quadruple patterning, the number of colors goes up. Triple patterning means you have three colors. Quadruple patterning means you have four. It gets more complex, because of the considerations of the different colors. Between the colors, there are tolerances that we need to comprehend. There are also discussions about the number of design rules escalating exponentially.

SE: TSMC is moving to self-aligned quadruple patterning and 1D layouts at 10nm. What do 1D layouts mean for foundry customers?

Low: What that means is you are enforcing unidirectional layouts. There are pros and cons. 1D means that once you enforce restrictions, you can control variability. At the same time, you have reduced the degree of freedom of laying out your IPs. Is that acceptable or not acceptable? You need to make sure whatever solution you provide to the customer, the customer has to buy into that.

SE: So it appears that multi-patterning is here to stay, at least until 10nm. Is that the case?

Low: We have to resort to immersion multi-level patterning technology. There is no other way around it. From there, we have to see how we can integrate EUV. All of us are waiting for the delivery of EUV. This technology has to be production worthy, with the right uptime of the tools and an economic throughput per day. We need EUV to eventually allow scaling, and die or transistor costs, to get back to their normal trajectory.

SE: Are there other lithography solutions on the horizon?

Low: There is a lot of research around DSA. The industry has also been working on multi-beam e-beam. Each one has its own pros and cons.