Good times ahead for the semiconductor industry, but some tricky issues that they will have to navigate in 2015.
This year more than 26 people provided predictions for 2015. Most of these came from the EDA industry, so the results may be rather biased. However, ecosystems are coming closer together in many parts of the semiconductor food chain, meaning that the EDA companies often can see what is happening in dependent industries and in the system design houses. Thus their predictions may have already resulted in their investment in tool development.
2014 was a pivotal year for the semiconductor industry in that it was the year when the ecosystem recognized that Moore’s Law, while still on track technically, has become irrelevant to all but a few chipmakers. 28nm has become the node where most people are likely to design for a significant time and the industry will start to improve that node in ways that we have not seen in the past. New processes, materials and devices will be developed for 28nm and packaging solutions such as 2.5D and 3D will become as important as process development.
The industry itself is doing so well that it is heading for a squeeze. “We see approximately 5% to 7% growth in semiconductor business for 2015 and 12% in the pure-play foundry business,” says Graham Bell, vice president of marketing at Real Intent. “Leading pure-play foundry TSMC will grow faster than the industry average and in 2015 its business will surpass that of all other pure-play foundries combined.”
When we couple that with a prediction from The 2015 Foundry Almanac, there could be trouble ahead. “Wafer-fab utilization at the four largest pure-play IC foundries will increase to an estimated 92% in 2014 compared to 89% in 2013 and 88% in 2012.” That does not provide a lot of headroom for growth unless the fabs start putting in extra capacity.
Other parts of the industry are also getting squeezed. “The worldwide market for DRAMs will rise 16% to $54.1 billion next year (2015),” according to DRAMeXchange forecasts. The company predicts that smartphones and tablet computers will drive that growth. Mobile DRAMs represent 40% of that, up from about 36% in 2014.
Sticking around at 28nm Synopsys is convinced that 28nm is here to stay. Three different people within the company were ready to defend their conviction. “28nm will have a very, very long lifespan,” says Marco Casale-Rossi, product marketing manager within the Design Group of Synopsys. “This will be strengthened by FD-SOI, which may be a very compelling solution if supported by foundries.”
Rich Goldman, vice president of corporate marketing for Synopsys, provides a little more background reasoning. “As the focus is on cost, low power and integration rather than on processing power, the favored processes will be established process nodes at 28nm and above. As it is the last process node that does not require double patterning, 28nm will be a particularly long-lived node, becoming increasingly popular. This will play well for foundries offering specialty processes. FD-SoI will likely be applied to extend the capabilities and longevity of 28nm.”
These sentiments are echoes by Navraj Nandra, senior director of marketing for DesignWare analog/mixed signal Intellectual Property, embedded memories and logic libraries within Synopsys. “The 28nm node is the main-stay of many devices and predictions are that this will be a “long node” meaning tape-outs will continue until 2020. The trend here is that some SoC developers are staying on 28nm rather than moving to finFET technologies due to costs or re-tooling their EDA and IP flows. To address this market, the semiconductor foundries are offering an array of 28nm technologies, the two most interesting are TSMC 28HPC and 28 FD-SOI.”
Moore’s Law is still alive
None of this means that Moore’s Law is technically dead and for some markets may even be seeing some acceleration. “The high-risk, high-reward transitions to new nodes at 16/14nm will be moving very quickly to 10nm and then 7nm,” believes Chi-Ping Hsu, senior vice president, chief strategy officer for EDA and chief of staff to the CEO at Cadence.
According to Nandra, three factors are driving fabrication technologies today. “The requirements for increased functionality, lower power and smaller form factors in mobile consumer devices are driving the demand for smaller technologies nodes such as 14nm and 10nm. Using these technologies they benefit from the significant reduction in power consumption, both dynamic and leakage. Another key benefit has been performance since these technologies use FinFET devices that have much higher drive. All the major semiconductor fabrication suppliers are projecting volume production in 2015 for 16/14 FinFET.”
The Intel roadmap already includes 10nm, 7nm, and 5nm, “enough runway to ensure that Moore’s Law will be in play for years to come,” says Goldman.
A close inspection of the memory process roadmaps reveals what they think is going to happen in 2015,” says Bell. “In 2015, we will see Samsung in volume production for 16/14nm DRAMS, followed at the end of the year by Micron and SK Hynix. For NAND flash we see a more aggressive roadmap, with 16/14 already at volume. The transition to 12/10nm processes will take over at the end of 2015.”
Getting to these nodes creates some mind-boggling numbers. “At 10nm we will be able to integrate more than 100 billion transistors on a single silicon die,” says Casale-Rossi,” and almost 10 trillion transistors at 1nm, towards the end of the next decade.”
Nandra sees that the only way to fill these chips is through IP. “SoC developers will use the opportunity to move to the next generation of interface IP protocols: USB 2.0 to USB 3.0; LPDDR3 to LPDDR4, PCIe 2.0 to PCIe 4.0. The 10-nm technology will only continue this trend with first tape-outs happening in 2015.”
Paul Pickle, president and chief operating officer for Microsemi, agrees about the importance of IP. “While the industry will still be working at advanced nodes down to 9nm, it will do so using IP blocks. However, there will be greater value in, say, a 28nm process backed by a rich IP portfolio than a 9nm process with no available IP.”
Casale-Rossi also puts it in perspective: “10% of design starts will be at 28nm and below in 2015. The future will not be decided by what is technically possible, but by what is economically affordable, on an application by application basis.”
Goldman provides another sobering note “These processes (this means 20/22nm and 14/16nm for 2015, along with the emergence of 10nm designs) are dominated by finFET. This assumes that the foundries are able to resolve yield issues.”
There certainly are hurdles that have to be overcome. Amit Gupta, president and chief executive officer for Solido Design Automation says that “manufacturing variation will become increasingly problematic in 2015. To ensure optimal design, development teams will focus both on resolving the increasing number of variation issues, and on reducing the simulations required.”
And when things do go wrong, it is important to be able to find out why. “With this trend toward smaller and smaller structures in today’s advanced processes, finding and analyzing the root cause of failures will become increasingly challenging,” says Taqi Mohiuddin, senior director of marketing for Evans Analytical Group. “Even one individual atom out of place is now causing device performance issues or defects. The device looks as though it has been built correctly, which is putting more and more pressure on failure analysis tools and techniques that investigate all the way down to the transistor level.”
Packaging set to explode
The industry has been waiting for 2.5D IC packaging to become an affordable reality. Many hoped that 2014 would be the year it would happen and yet they were frustrated at the slow rate of development. They are not willing to back down.
“Multi-die designs, especially with interposers, will start to become more mainstream,” says Aveek Sarkar, vice president of product engineering and support at Ansys-Apache. “This will be true especially for applications that need heterogeneous integration support to benefit from advanced processes for digital circuits and mature technologies for analog circuits.”
While most companies keep an eye on stacked die, the big question is timing. “Technology solutions are in place, but we’re just not seeing the pull,” says Steven Pateras, product marketing director for test at Mentor Graphics. He adds that there are still some big questions to resolve before this packaging approach gets rolling.
“How much testing do you do at the wafer level versus what you do at the package, whether it be 2.5 or 3D packages? The sensitivities are somewhat different at 3D because you are stacking multiple die and the total yield issue is more important,” Pateras notes. “The cost of the package is more important. There’s definitely a push toward going to known good die in 3D-IC. The cost of spending more time at a wafer level becomes more compelling. When people actually start doing 3D you will definitely see a move away from ‘probably good die’ to ‘known good die.’ We’re already seeing a move toward known good die for specific application areas anyway, despite the lack of 3D—automotive in particular. There’s a much greater thrust on quality now for the automotive sector, which is exploding.”
But stacked die continues to draw attention, and it should by no means be counted out.
“Semiconductor companies must increasingly be technology-agnostic when it comes to fabrication technologies,” says Pickle. “Innovation will continue to move past a myopic focus on Moore’s Law in a growing range of applications – not simply because scaling no longer delivers the same predicted economic benefits, but because so many of today’s system-level integration challenges require more than just smaller transistors, including the difficult combination of multiple types of analog, RF and mixed-signal devices functions into feature-rich SoCs that are built using multiple process technologies and advanced packaging techniques. An increasingly attractive option will be 2.5D packaging supporting 2,000 or 3,000 connections between dies.”
This is not a time when EDA appears to be holding things back. “The lines between PCB, package, interposer, and chip are being blurred,” points out Hsu. “Having design environments that are familiar to the principle in the system interconnect creation, regardless of being PCB, package, or die-centric by nature, provides a cockpit from which the cross-fabric structures can be created and optimized. Being able to provide all of the environments also means that data-interoperable sharing is smooth between the domains. Possessing analysis tools that operate independent of the design environment offers the consistent results for all parties incorporating the cross-fabric interface data.”
But what will it take to get the ball rolling? The increasing importance of emerging markets may provide the economic incentive. “Automotive, health care, industrial and sensors will remain at the established technology node,” says Casale-Rossi. “They will perhaps be looking for alternatives such as 2.5D and 3D-IC, silicon photonics, among others, to improve integration and performance.”
Today, 2.5D and 3D-ICs are still taxiing while the supply-chain is being sorted out. “3D will still be over the horizon in 2015,” says Mike Gianfagna, vice president of marketing at eSilicon, “but interposer design will become more relevant in 2015. It might take another year to reach the mainstream however.”
Hsu suggests that “the foundry encroachment into the OSAT (outsourced assembly and test) space has begun with silicon-based 2.5D interposer technology and through silicon via (TSV) 3D die stacking offerings. As the pitches get finer on organic substrates and pricing on silicon options comes down, the foundries and the OSATs will be on an innovation spree to vie for dominance.”
But not all see this as the certain path forward. Bernard Murphy, chief technology officer at Atrenta, sees another possibility. “Intel is actively working on flip-chip and bump interconnects for die stacking, rather than TSVs. This is claimed to be simpler, lower cost and higher density than a TSV approach.” Murphy assumes this limits stacking to two die—maybe. “That hardly seems like a major limitation for most designs these days—and you presumably could still extend to side by side stacks on an interposer if needed.”
Murphy also expects more competition from monolithic 3D technologies. These are two or more layers of active components stacked above the same bulk silicon. “According to Qualcomm, TSV architectures are not really solving the interconnect issue and are costly. Monolithic 3D-ICs use much smaller vias, which can provide both more and finer-grained connections. This can provide a one-process-node advantage along with a 30% power savings, 40% performance gain, and 5% to 10% cost savings.”
Markets, economics and politics
Emerging markets, such as the Internet of Things are highly cost-sensitive markets, but their complexity is simplified because of the lower demand on data processing.
“Typically these devices are designed with fewer metal layers, to save on cost, and the IP requirements are also simplified compared to the high-end application processors,” says Synopsys’ Nandra. “This brings on new design challenges where cost is a determine factor. A small amount of code storage is required in these applications and semiconductor foundries are qualifying embedded flash technologies to meet these requirements. Power is also a key consideration and the trend by here is for the foundries to offer ultra low-power technologies. Since the data processing speed is not a key consideration for these devices but leakage power is, these high threshold devices will become popular.”
Bell sees another impact coming from politics. “The joint United States-China announcement of an end to China’s tariffs of up to 25% on advanced semiconductor components came as a surprise this past November.” Product groups for which tariffs will be eliminated include high-end medical equipment and game consoles, which only just recently became available to consumers in China. Bell explains the impact. “As with any tariff, local businesses are protected from foreign competition to give them an edge in economic growth. China certainly wants to promote its high-technology sector. However, big companies such as Lenovo and Huawei that are headquartered in China found themselves at a disadvantage when trying to compete with foreign companies on product cost. Both of them rely on imported ICs to build their systems.”
Bell says this will benefit large electronics systems companies, while China’s semiconductor foundry sector may be the loser. “SMIC is the leading Chinese foundry, with approximately 40% of its business from domestic customers. Its revenue in terms of dollars-per-wafer is much lower than other leading foundries because more than 80% of its business is in geometries larger than 45nm. With customers turning to foreign suppliers that can offer more leading-edge processes, SMIC may be forced into a consolidation with another leading pure-play foundry.”
The net result is that the cost of devices made in China may be lower and that will add up to even tougher consumer product competition.
[Last year, Semiconductor Engineering reviewed the 2014 predictions to see how close to the mark they came. You can see those in part one and part two of the retrospective. We will do the same with their predictions this year.]