Adding a Z axis is just the beginning.
Ever since the publication of Gordon Moore’s famous observation in 1965, the semiconductor industry has been laser-focused on shrinking devices to their practical, and more recently, impractical limit.
Increasing transistor density has encountered a number of problems along the way, but it also has enabled us to put computers—which once filled specially built rooms—onto the desktop first, and then into our pockets. And all of this has been done for less money than ever before and with an acceptable level of reliability.
Looked at over time, this can be plotted as a relatively straight line. Costs have dropped every two years, at least until 28nm, and performance per watt has improved along with it.
But after 28nm, this equation no longer works on any level. While vertical transistors and 3D memories are indeed a monumental technological achievement, they are only part of the picture about what needs to be included in future designs—and what needs to be considered. There are issues with routing congestion, signal integrity, thermal effects, electrostatic discharge, electromigration, leakage current, dynamic current density, lithography limitations and multi-patterning, new materials such as cobalt for interconnects, mask alignment—and that’s just a portion of the list.
For all these reasons and others, advanced packaging is garnering much more interest. Fan-out wafer-level packaging has seen its first mass adoption with the iPhone 7 application processor, which is the centerpiece of one of two markets that have been propelling Moore’s Law—the other is servers. The expectation is that Moore’s Law will continue for a smaller subset of features, notably the main CPU, which has much more regular structures than an SoC, and probably an embedded FPGA, which will allow more programmability to be built into the logic. Those likely will progress to 5nm and 3nm, and maybe beyond, because more transistors will be required to process a surge in data as the physical world increasingly is connected to the digital world.
But not all of the semiconductor components need to shrink to the same level as the core logic, and this is where advanced packaging gains its footing. Fan-out wafer-level packaging appears to be the best choice for many applications that require the advantages of scaling without the litany of issues related to putting everything on a single die. 2.5D seems to be the top choice for the highest-performance applications, such as networking or high-performance computing, where the cost can be absorbed into the system. But at some point, that will likely move to 2.1D, because an organic interposer is far less expensive, easier to work with, and non-proprietary.
For chipmakers, this creates some initial problems. There is a steep learning curve for packaging. In many cases, the logic will still be created at advanced process nodes, even though other pieces can be created at older nodes. And while some tools exist to create these packaged systems, there are gaps in the tool flows and in the methodologies used to apply them. All of that needs to be filled out, which will take some time. Packaged solutions are being created today, but it’s not as straightforward as developing an SoC at 16/14nm.
Once those pieces are in place, though, the rules for how these systems are designed will become much more flexible. Design rules from the foundries, which are in place to improve yield, have been getting progressively more restrictive at each new process node. Packaging options act like a reset button for system-wide design. While logic will still need to conform to those rules, chips developed at older nodes can be included in a package and those are not subject to the same rules do not. There will be new rules for packaging, of course, but they are unlikely to be anywhere near as rigid as for 7nm finFET designs. The challenge will be less about yield and more about testability and reliability.
Moreover, the number of options available for putting pieces together will be huge. Rather than just side by side or vertical, this ultimately will become a multi-layer stack that can be pieced together in all directions. And that opens up some interesting possibilities for what systems can achieve in terms of power, performance, cost and even security. This is a whole different way of looking at a problem, and one that is long overdue for semiconductor engineering.
Betting On Wafer-Level Fan-Outs
Chipmakers focus on packaging to reduce routing issues at 10nm, 7nm. Tool and methodology gaps remain.
Making 2.5D, Fan-Outs Cheaper
Standards, new materials and different approaches are under development to drive 2.5D, 3D-ICs and fan-outs into the mainstream.
Packaging Wars Begin
OSATs and foundries begin to ramp offerings and investments in preparation for mainstream multi-chip architectures.