More Lithography Options?

Lithographers could soon have some new, and potentially disruptive, options on the table, but will they work?


Lithographers face some tough decisions at 10nm and beyond. At these nodes, IC makers are still weighing the various patterning options. And to make it even more difficult, lithographers could soon have some new, and potentially disruptive, options on the table.

On one front, the traditional next-generation lithography (NGL) technologies are finally making some noticeable progress. For example, ASML’s power source for extreme ultraviolet (EUV) Lithography recently reached a new milestone by generating 90 Watts of power, compared to a mere 10 Watts a year ago. At the 90 Watt level, EUV could potentially move from the lab into the pilot line, but there are still a multitude of challenges with EUV.

The other NGL candidates, such as directed self-assembly (DSA), multi-beam e-beam and nanoimprint, are also making strides.

But in what could shake up the landscape, Intel Corp. is proposing a new patterning-like option for 7nm and beyond—selective deposition. Still in the R&D stage, selective deposition is an emerging form of deposition that helps build devices from the ground up. In theory, a tool can be used to selectively deposit materials, namely metals on metals and dielectrics on dielectrics, on a device.

Selective deposition could be used with current lithographic techniques to help pattern vias and other structures. “(Selective deposition) is a convergence,” said Yan Borodovsky, a senior fellow and director of advanced lithography at Intel. “It’s a convergence of surface chemistry, pre-cursor chemistry, thin films, patterning and lithography. It also may require a different etch.”

The technology could help solve one of the challenges in lithography—edge placement error (EPE). EPE is measured as the difference between the intended and printed features in a layout. EPE control becomes more difficult in chip scaling. “Scaling will continue to go on and will continue to offset wafer costs, as long as we master edge placement error,” Borodovsky said. “When I look at the existing approaches, there is EUV or the other NGLs. Each of them might or might not be able to help with the edge placement problem. So we really need to look at something else. Fundamentally, selective growth is supposed to place edges exactly where you want them, irrespective of what lithography technique is involved.”

Still, the questions are clear. Is selective deposition a viable patterning candidate? What’s going on with the NGLs? And, of course, what will happen at 10nm and beyond?

EUV vs. 193nm
As it stands today, chipmakers will extend 193nm immersion lithography with multiple patterning down to 10nm. But the picture is cloudy at 7nm and beyond. At 7nm, Intel plans to use 193nm immersion with multiple patterning. The other foundries want EUV at 7nm, but it’s still unclear if the technology will be ready in time. So, chipmakers are devising an immersion/multi-patterning strategy for 7nm as well.

All told, the insertion point for EUV remains a moving target. ASML has shipped several EUV tools in the field. By mid-2015, ASML plans to ship a new version of its production-worthy EUV scanner, dubbed the NXE:3350B. It will take around a year before the results are made public.

EUV is making progress after years of delays, but there are still issues with the power source. Today, the EUV power source can generate 90 Watts of power. But still, the availability of ASML’s current EUV tool is only 55%, resulting in a throughput of about 40 wafers per hour, according to lithography expert Chris Mack.

ASML and Gigaphoton are separately developing EUV power sources that could reach 250 Watts in the future. At 250 Watts, EUV could be used in high-volume production.

But 250 Watts may not be quite enough. For example, GlobalFoundries compared EUV and rival 193nm immersion with triple patterning in a simulated environment. The goal was to see how much EUV power would be required to match or beat the throughput of triple patterning. In the experiment, GlobalFoundries printed 22nm half-pitch contacts. The EUV resist had sensitivities of 30mJ/cm2.

“In order to be cost effective with immersion triple patterning, we are going to need source power somewhere between 350 and 400 Watts,” said Harry Levinson, senior fellow and director of strategic lithography technology at GlobalFoundries. “So there needs to be substantial progress of the EUV light sources to make EUV lithography cost effective against triple patterning.”

On the bright side, EUV could simplify the patterning process, as compared to optical. But chipmakers may require EUV with multiple patterning at 7nm and beyond, which could add more cost to the equation.

Ultimately, though, chipmakers hope to use both EUV and immersion/multi-patterning in a hybrid approach at 7nm and beyond. “Patterning is evolving into two parts. For line/space, 193nm is probably going to be used for a while,” said Uday Mitra, vice present and chief technology officer for the Etch Business Unit at Applied Materials. “The tricky part is the cutting. How do you do all of the cuts? With 193nm, you can’t do all three or four cuts simultaneously. EUV can do that, at least maybe for the 7nm node, along with some tricks.”

All told, lithographers face some challenges. “Clearly, no one is giving up on EUV,” said Brian Trafas, chief marketing officer at KLA-Tencor, “but multiple patterning will be a key solution. Obviously, the challenge is that you are adding more process steps, costs and cycle times. When people talk about quadruple patterning, you really start to have a cost concern. If I could do EUV on those steps, that would help dramatically. So everyone is interested in EUV, but it’s a question of the timing.”

There are other challenges in the patterning flow, namely in process control. “When we break down the sources of error, there are traditional litho (errors), overlay errors and scanner CD errors. And within the litho process itself, there may be process variations. And then, there are other sources of errors in the fab,” Trafas said.

Multi-beam, imprint and chemistries
Meanwhile, there are other patterning options. For example, the industry is using single-beam e-beam for direct-write lithography applications, mainly for niche-oriented devices. Direct-write does not require an expensive photomask. But the throughputs for single-beam e-beam are too slow, making it too expensive for volume IC production.

To solve the throughput issues, Mapper and Multibeam have been separately developing tools that make use of multiple beams. But like EUV, multi-beam is delayed and is still not in production amid a number of challenges. “The fundamental physics are there for multi-beam,” said Aki Fujimura, chairman and chief executive of D2S. “The strength of e-beam is the depth of focus. The weakness of e-beam is that it takes time (in terms of throughput).”

Still, there is some progress. Last year, Mapper Lithography installed the world’s first pre-production multi-beam tool at CEA-Leti. Mapper’s tool is called the Matrix 1.1.

Now, Mapper and CEA-Leti are getting the tool ready for production. With its system, CEA-Leti is working on the beam yield and handling system. With a separate machine, Mapper is developing the blanker module.

By year’s end, the blanker and other components will be integrated within the Matrix 1.1 tool at CEA-Leti. All told, Matrix 1.1 will provide a 32nm half-pitch resolution, a 10nm overlay and a modest throughput of 0.5 wafers an hour.

Originally, the goal was to devise a 13,000 beam system. Now, the goal is to get 1,300 beams up and running, which enables a throughput of one wafer an hour. “The reason why we won’t have one wafer per hour by the end of the year is because the number of beams is not at 100% yet. It’s maybe between 70% and 90%,” said Laurent Pain, patterning program manager at CEA-Leti.

In addition, Mapper appears to have re-positioned the Matrix 1.1. Instead of competing at the leading edge, the tool is geared for ASICs and related applications in more mature nodes.

Another NGL technology, nanoimprint, is making also progress, at least in the NAND market. Thanks to multiple patterning, NAND flash vendors have extended planar NAND down to the 1xnm node. One NAND supplier, Toshiba, has been using nanoimprint lithography in conjunction with 193nm immersion. SK Hynix also recently jumped on the imprint bandwagon.

Both Toshiba and SK Hynix are using nanoimprint tools from Canon Nanotechnologies (CNT), formerly Molecular Imprints (MII). In 2014, Canon acquired the semiconductor unit of MII, a supplier of nanoimprint tools.

Nanoimprint enables resolutions below 10nm. “Low cost of ownership is also an advantage for nanoimprint,” said Toshiaki Ikoma, executive vice president and chief technology officer at Canon.

The knock on nanoimprint is defectivity, overlay and throughput. To address the issues, CNT has rolled out a new four-station cluster system that enables a throughput of 60 wafers an hour. It has a 6nm overlay in a mix-and-match setting.

Like nanoimprint, DSA might have more luck in the memory market. DSA is not an NGL tool per se. It makes use of block co-polymers to reduce the pitch of the final printed structure.

Chipmakers are all working on DSA in R&D pilot lines. DSA could be ready at 7nm or 5nm. “The materials are getting there, if not there already,” said Ralph Dammel, chief technology officer of EMD Performance Materials.

Still, DSA faces some challenges, namely defectivity and other issues. “What comes back to bite us is the fact that the supporting technologies, or the infrastructure for DSA beyond the materials side, has not been fully developed,” Dammel said. “The question is how do I integrate DSA into designs? And what about metrology with DSA? These questions have not been answered.”

So where does DSA go from here? “What this means is that the first implementations for DSA will be for highly regular patterns, maybe in memory. Logic doesn’t need DSA for a while,” he said.

Like DSA, selective deposition could be classified as a complementary technology. Selective deposition involves the use of special chemistries and novel atomic layer deposition (ALD) and molecular layer deposition (MLD) tools. In the lab, researchers have used the technology to deposit self-assembled monolayers and organic films.

“There are many ways to think about selective deposition,” said Girish Dixit, vice president of process applications for Lam Research. “There is selective deposition today in the backend, when you deposit cobalt as a capping layer. Doing selective deposition for metal on a metal or dielectric on a dielectric is another way. If you can do a deposition like that, you maybe can get into a position where you don’t have to think about edge selectivity in the traditional way.”

Still, it’s too soon to say if selective deposition will solve the problems in patterning, according to Applied’s Mitra. “It’s still more in the path finding stage,” he added.

Selective deposition, along with DSA, EUV, nanoimprint and immersion, are all candidates for 5nm. But it’s way too early to predict what may happen at 5nm. And for that matter, it’s still unclear if the 5nm node will even happen at all.

  • TravisJSays

    EUV – the Gallium Arsinide of lithography. When oh when will it get out of the lab?