Semiconductor manufacturers are still betting big on EUV, but it’s no longer their only bet.
By Mark LaPedus
It’s the worst-kept secret in the industry. Extreme ultraviolet (EUV) lithography has missed the initial stages of the 10nm logic and 1xnm NAND flash nodes.
Chipmakers hope to insert EUV by the latter stages of 10nm or by 7nm, but vendors are not counting on EUV in the near term and are preparing their back-up plans. Barring a breakthrough with EUV or other technology, IC makers will likely use today’s 193nm immersion with multiple patterning at 14nm, 10nm and perhaps beyond. “10nm will be optical,” said Ajit Manocha, chief executive of GlobalFoundries. “We have evidence that we can do 7nm with immersion.”
GlobalFoundries, for one, is laying the groundwork if EUV is ready by 10nm. “We are keeping our ground rules migrate-able to EUV,” added Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries.
Chipmakers are keeping their options open for good reason—extending optical comes with a penalty. The shift from single patterning at 28nm to multiple patterning at 20nm is projected to increase lithography costs by up to 56%, according to Barclays Capital. Consequently, the overall cost-per-transistor curve is in danger of slowing or derailing.
Lithographers, who seem to achieve miracles when the chips are down, are determined to stay on Moore’s Law. “The cost of processing might go up with multiple patterning, but cost-per-transistor does not,” said Yan Borodovsky, a senior fellow and director of advanced lithography at Intel.
The ability to stay on the critical cost-per-transistor curve puts enormous pressure on the lithographic supply chain, which includes the EDA houses, materials suppliers, mask shops, and tool vendors. In response, Nikon is quietly shipping a faster scanner for 10nm. Lithographers also may resort to some new patterning tricks. The wild card is directed self-assembly (DSA), an alternative lithography technology that makes use of block copolymers to enable fine pitches.
For years, there have been fears that optical lithography would run out of gas, prompting the need for a new next-generation lithography (NGL). EUV emerged as the leading NGL candidate. The other NGLs, maskless and nanoimprint, are also in the hunt.
EUV, a soft X-ray using 13.5nm technology, is attractive because it keeps the industry on a single-exposure path. But EUV has encountered several delays due to the lack of adequate power sources, defect-free photomasks and photoresists.
The current throughput for ASML’s EUV tools is less than 10 wafers an hour (wph). At one time, ASML hoped to ship an EUV scanner with a 150-watt source by mid-2012. A 150-watt source equates to a more acceptable throughput of 69 wph.
Recently, the 150-watt source was delayed again and pushed out to mid-2014. The source is being developed by Cymer, which itself is being acquired by ASML. Separately, Intel, Samsung and TSMC have recently invested in ASML to help fund ASML’s efforts in EUV and 450mm.
ASML is still targeting EUV for mass production in 2014, but the industry isn’t taking any chances and will extend 193nm immersion—at a price. On average, there are 37 lithography layers processed for 32nm/28nm chips, according to Barclays. Of those, there are 14 critical layers processed using 193nm immersion scanners.
In total, there are 38 lithography exposures at 32nm/28nm, 15 of which are immersion exposures, with only one multiple patterning step in the flow, according to Barclays. In terms of lithography equipment costs at 32nm/28nm, a foundry spends an estimated $17 million per 1,000 wafer starts per month (wspm).
In comparison, there are 40 lithography layers for at 22nm/20nm chips, 19 of which are critical layers. In total, there are 52 lithography exposures at 22nm/20nm, 31 of which are immersion exposures with 11 multiple patterning steps. All told, a foundry is expected to spend $27 million per 1,000 wspm in lithography costs, according to the firm.
Lithography steps and costs will soar at 14nm and beyond. In response, chipmakers already are prepared for the dreaded multiple patterning era. NAND flash vendors, for example, are using a multiple patterning technique called sidewall image transfer (SIT), sometimes called self-aligned double patterning.
In logic, vendors have or will implement one of the various flavors of multiple patterning: SIT, litho-etch-litho-etch (LELE) or self-aligned vias. Intel, for one, is embracing a concept called complementary lithography, which involves an SIT flow. Other logic vendors are following a similar path with various nuances.
Today, Intel is using 193nm immersion with multiple patterning at 22nm, with plans to extend that to 14nm. At 22nm, Intel’s processors are based on finFETs. “For the 22nm node, our fin is finer than what can be done with simple patterning. It’s done with pitch division. We still stay on an historical cost-per-transistor trend,” said Intel’s Borodovsky. “Our 14nm technology is also pitch-divided technology. We project our cost-per-transistor will remain on the trend.”
For 11nm, Intel is looking at quintuple exposure. As part of the process, there are two steps, gratings and line cuts, to pattern designs. Using 193nm immersion, the first exposure is used to make the gratings. The remaining four exposures are used to cut the pitch-divided lines.
To perform the cut step, Intel is evaluating several options: 193nm immersion; DSA, EUV; or direct-write e-beam. So far, there is no clear winner—193nm immersion is challenging, but DSA, EUV and maskless are not ready for mass production.
“I believe we can extend (193nm immersion) for many years,” Borodovsky said. “We also have a dual wave lithography roadmap. It means we will extend existing technology as long as possible. And we will bring in new technology when it is available and affordable.”
Using NGL has some advantages over optical. “If we use EUV, we will use one mask to do the gratings and another mask to break those continuities. If we use direct write, we don’t use any masks,” he said.
Another technology, DSA, potentially could extend 193nm lithography beyond 10nm. As before, the challenges for DSA are defects and the lack of a design infrastructure. The new gap for DSA is non-destructive metrology as a means to inspect the morphologies in the patterns.
DSA materials providers have said DSA would be ready at 10nm, but there are signs the technology may get pushed out. For example, IBM is targeting DSA for 7nm, said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM.
“DSA is making progress,” said Intel’s Borodovsky. “But let’s say we use DSA. If you look at a SEM, you look at the top. Everything may appear perfect. But the cylinders could also change their shapes from top to bottom. You have to have a cross section. So, it’s very difficult to do a cross section of 15nm holes or cylinders. You can do complicated X-ray metrology. For this, you need a synchrotron source, which is not practical.”
Etch is another roadblock. Some of the cylinder morphologies in DSA structures are uniform while others are not. “Some would etch to the bottom. You might also have cylinders that are etched in the wrong place. That’s an edge-placement error,” he added.
Until NGL is ready, chipmakers are stuck. “I don’t think the industry has given up on EUV. EUV will be in play, but it will be in limited use,” said Hamid Zarringhalam, executive vice president at Nikon Precision. “But for 10nm, almost all logic vendors are looking at immersion technology. Customers are even looking at extending immersion beyond 10nm.”
To keep up with the increase in multiple patterning steps, ASML and Nikon are shipping faster scanners. Nikon, for one, has begun shipping the NSR-622D, a 193nm immersion scanner for the 10nm node. The tool has a throughput of 200 wph. In addition, Nikon is also developing a separate 193nm immersion tool for the 450mm wafer size.
Besides lithography scanners, there is an urgent need for new and faster e-beams in photomask production. Mask making itself is quickly turning into a fine and precise art. In quadruple patterning, for example, the patterns must be split into four masks.
“One mask has to be perfect in terms of CD uniformity, linearity and defects. The other three masks have to be exactly the same,” said Amitabh Sabharwal, general manager for mask etch products at Applied Materials. “When you start going down to the 16nm node, the CD uniformity targets become very, very tight. We’re talking in the range of 1nm. And on top of that, the defect levels might be very tight. Your systematic uniformity has to be zero. Essentially, everything must be flat.”
Looking into his crystal ball, lithography expert Chris Mack predicts that the industry will embrace new design methodologies such as 1D layouts. “We will see more interaction between lithography and design,” Mack said. “The reality of what we can accomplish lithographically will have more influence on the way designs are implemented. In fact, this might not be a bad thing. The switch from arbitrary designs to more (1D-like layouts) is turning out to have less impact on chip area than many people expected. And they are lithographically friendly.”
The industry also will embrace complementary lithography or hybrid approaches. “There is no doubt in my mind that optical will go forever,” he said. “But I do think there is a possibility of hybrid lithographic approaches that are optimized for specific types of patterns. Complementary lithography is a powerful technique and makes the most sense. All of the (NGLs) have a lot of potential, but they are not being developed in the timeline the industry needs.”