Re-Engineering The FinFET

Shapes, sizes, pitches, materials and manufacturing processes all are being revamped in preparation for the next-generation of transistors.

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The semiconductor industry is still in the early stages of the finFET era, but the transistor technology already is undergoing a dramatic change. The fins themselves are getting a makeover.

In the first-generation finFETs, the fins were relatively short and tapered. In the next wave, the fins are expected to get taller, thinner and more rectangular in shape. This, in turn, is expected to provide more drive current in the finFET, enabling faster chips at lower power.

This isn’t so easy, though. Re-engineering the fins in finFETs is both challenging and costly. There are a number of design and manufacturing tradeoffs. And it requires a multitude of difficult fabrication steps, which fall under a loosely defined segment called fin engineering.

Fin engineering is a critical piece of the overall finFET puzzle. “Fin engineering will become significant,” said Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries. “But it’s not getting any easier in other respects. The dimensions are getting smaller. You also have to integrate various elements, such as spacers and source/drain structures. The question is how can we squeeze these elements into the device and still provide a higher performance.”

In any case, the questions are clear in the fin engineering segment alone. How tall and thin will the fins get at 16nm/14nm and beyond? What will they look like? And what does this all mean in the big finFET picture?

Fin engineering
For decades, the industry has incorporated the traditional planar transistor in designs, but this technology is running out of gas at 20nm due to short-channel effects. So the industry is moving toward finFETs in which the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

Generally, a finFET could have two to four fins in the same structure. The fin pitch is the sum of fin width and the space between fins. Chipmakers hope to scale the fin pitch by 0.7X at each node. The lithography process determines the fin pitch.

Meanwhile, each fin has a distinct width, height and shape. The fins are developed using deposition, etch and other steps. And, of course, the gate also has various characteristics, namely the gate length.

In one finFET production flow, the substrate initially goes through various lithography steps, namely spacer-based patterning. In this process, spacer-like structures are patterned on the substrate. Then, between these structures, an etcher carves out vertical trenches down into the substrate, thereby forming fins. “Then, you change the etch recipe. You give it a slight taper angle and then etch down. This becomes my STI (shallow trench isolation). The top becomes my fin,” said Reza Arghavani, a fellow at Lam Research. “The fin and STI are done in one etch. It didn’t used to be that way in planar. So in this portion, it’s slightly simpler.”

Then, the spaces are filled with oxide using a deposition process. The top portion is polished and then the device undergoes a recess etch step. Finally, a gate oxide is deposited, followed by the formation of the gate.

Clearly, the flow is challenging. Patterning and etch are the most difficult steps. “You must control the (fin width) with billions of transistors involved. You also have to control the fin height. I also have to control the STI height,” Arghavani said.

Cost is another factor. In fact, citing lithography costs and other factors, Intel has stated that its overall wafer costs increased at 14nm. “The process is getting more complicated. It may require more steps,” said Adam Brand, senior director of the transistor technology group at Applied Materials. “But if you can get twice as many transistors per unit area, you can (offset) the more expensive wafer cost.”

Despite the challenges, Intel rolled out the world’s first finFETs in 2011. Launched at 22nm (the last node at which double patterning is not required), Intel’s first-generation finFETs had fin shapes that resembled trapezoids. The technology had a fin pitch of 60nm and a fin height of 34nm. The fin width was around 13nm.

Recently, Intel rolled out its second-generation finFET technology at 14nm. The fin pitch and height are both measured at 42nm. The fin width, according to some estimates, is about 8nm. “(Taller and thinner fins) improve the electrostatics of the fins,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel. “Maybe more importantly, it has better performance at low voltage, partly because it has lower variability.”

At 14nm, Intel also moved to rectangular fins for good reason. Trapezoid-based fins require more doping, possibly leading to variation. “In all cases, the straight fin performs better than the tapered fin,” Lam’s Arghavani said. “That has to do with the electrostatics. The sub-threshold slope is much better.”

Meanwhile, IBM, TSMCand the GlobalFoundries-Samsung duo are ramping up their initial finFETs at 16nm/14nm. (GlobalFoundries licensed Samsung’s 14nm finFET technology.) These vendors haven’t revealed the exact dimensions of their finFET structures, but the trends are clear—tall, thin and rectangular fins.

Commenting on the general trends in the industry, GlobalFoundries’ Banna said that thinner fins provide several advantages. “The skinny fin gives you off-state leakage control, because the gates are closer at the top as well as the bottom of the fin. It gives you good control on the channel. This means the device can turn on and turn off with a sharp transition, meaning your sub-threshold slopes are better and the leakage is lower,” Banna said.

Regarding the fin height, the issues become more complex. In fact, the chipmaker determines the overall height of the fin for a given IC design. IC designers would like taller fins to enable more drive current, but there are some practical limitations. The fin height, of course, must adhere to the design rules. And taller fins could also lead to an increase in unwanted capacitance.

IC designers must make some tradeoffs. “Once you fix the fin pitch based on your scaling requirements, then the fin height for a given product is determined. Fin height is something we can control in the fab,” Banna said. “But if you increase the fin height, you must look at the rate in which current improves versus the capacitance. And then you have to find an optimal place for the fin height.”

For example, Intel’s processors tend to have high drive currents. “They need a device with more current at the same Vdd. So, they went to a taller fin and brought the fins much closer. Bringing the fins closer also reduces the capacitance,” he added.

There are also tradeoffs in the fab flow. “It’s not simple to say taller is better,” Applied’s Brand said. “Of course, taller is better if you are the circuit designer. But from the process manufacturing side, taller fins are more difficult. There are trade-offs in terms of the difficulties of doing the etch and gap fill steps.”

What’s next?
The fin engineering trends are apparent at 16nm/14nm, but what about the 10nm node and beyond? The fins are expected to get thinner and closer together. The fin height could go in two separate directions—taller or remain constant.

For now, the industry is leaning towards one direction—keep the fin height relatively constant, but change the channel material. In fact, the industry is looking at adding a mix of germanium for pMOS at 10nm and/or 7nm. This way, chipmakers can get a performance boost, while avoiding unwanted capacitance. “So, we make the fin as tall as the design allows,” Lam’s Arghavani said. “But why not change the material to something other than silicon, which intrinsically has a higher electron and hole mobility. That’s the focus of our industry right now for the next node, maybe 10nm or 7nm.”

Others agree. “You want [the fins] to get narrower to scale the gate dimension. That’s a given. For fin widths, we’re talking about 10nm going to 6nm or 7nm wide,” said Terry Hook, senior technical staff member at IBM. “Taller fins might look good on a TEM. But it’s not obvious to me that the fins need to be taller. I am more concerned about power density, getting that current out and really using it.”

Based on the current roadmaps, meanwhile, chipmakers will scale today’s silicon-based finFETs to 10nm. But at 7nm, the industry could move in two directions. There is one school of thought that today’s finFETs will run out of gas at 10nm, prompting the need for a new transistor architecture at 7nm.

But the momentum is building for another school of thought, in which today’s finFETs will scale to 7nm. In this scenario, chipmakers are looking at shrinking the fin width from 8nm at the 10nm node to around 5nm at the 7nm node. “People have shown good characteristics down to about a 5nm wide fin,” said Chris Hobbs, process, materials and ESH program manager at Sematech. “The question is can you get a nice fin with a good line-edge roughness and smoothness.”

Still to be seen, however, is just how tall a fin will get at 7nm. “It’s too early to tell,” Hobbs said. “It’s an optimization problem. You need to look at what drive current you need out of that and the performance of the device.”

There are other considerations as well. “Of course, limitations are posed by practical process challenges and control, as well as fundamental device issues of very thin channels,” said Aaron Thean, director of the logic program at IMEC. “This includes defects, mobility loss, and an access resistance increase. In addition, making fins taller adds to the less-desired FEOL parasitic coupling capacitances as well.”

So to what extent can the industry re-engineer the fin at 10nm and beyond? The answer revolves around another question—How far can the industry extend the finFET? FinFETs could hit the wall at 5nm. “You can go from 8nm to 5nm. That still provides a way of reducing the fin width and getting to lower gate lengths,” Applied’s Brand said. “But at 5nm, according to simulated work, people see that quantum mechanical confinement effects begin to change the behavior of the carriers in the channel. This will cause a lot of threshold variations. Below 5nm, we have to worry about a device control problem coming in.”

At that point, the industry may require a next-generation transistor technology. Chipmakers are exploring several options. All told, this will bring in more unknowns, if not another makeover, for the transistor.