New Deep Learning Processors, Embedded FPGA Technologies, SoC Design Solutions


Some of the most valuable events at DAC are the IP Track sessions, which give small and midsize companies a chance to share innovations that might not get much attention elsewhere. The use of IP in SoCs has exploded in recent years. In a panel at DAC 2017, an industry expert noted that the IP market clearly was growing even faster than EDA itself, due to the fact that more and more chip mak... » read more

By the Power Vested in Me, I Now Pronounce You (The SoC Designer)…


…Doomed. Well, maybe that’s a little harsh, but your job won’t be getting any easier; that “happily ever after” may be harder to achieve than you think, and there are a number of reasons why. And by “me” (of vested power), here I’m really talking about the power of the consumer market as a whole and our collective insatiable demand for newer, shinier…well, just plain “coo... » read more

Data Converters IP For Automotive SoCs


Automotive applications place demanding requirements on IP designers and SoC integrators to meet all mandated reliability and functional safety requirements. A good understanding of such requirements and how to efficiently implement them in the SoC enables integrators to break down the challenges into manageable pieces while leveraging the characteristics (and qualification) of the integrated I... » read more

The Implementation of Embedded PVT Monitoring Subsystems In Today’s Cutting Edge Technologies


This new whitepaper from Moortec takes a comprehensive look at the Implementation of Embedded PVT Monitoring Subsystems in Today’s Cutting Edge Technologies and how this can benefit today’s advanced node semiconductor design engineers by improving the performance and reliability of SoC designs. With advances in CMOS technology, and the scaling of transistor channel lengths to nanometer (nm)... » read more

Move Data Or Process In Place?


Chip architectures, and even local system architectures, long have found that the best way to improve total system performance and power consumption is to move memory as close to processors as possible. This has led to cache architectures and memories that are tuned for those architectures, as discussed in part 1 of this article. But there are several tacit assumptions made in these architectur... » read more

Challenges And Trends In SoC Electromagnetic (EM) Crosstalk


Electromagnetic Crosstalk analysis is emerging as a fundamental necessity as a component of electronic system development. With the advent of advanced technologies and System on-Chip (SoC) architectures, ignoring electromagnetic crosstalk is highly risky resulting in significant delays in reaching the market on time as well significant cost over runs. This paper provides an overview of the stat... » read more

Prototyping Building Blocks


Lego has existed for 85 years. The company was founded August 10, 1932, and after all these years, the concept of building structures big and small still hasn’t lost any of its charm. For my children, now 10 and 12, it is probably the most played with toy throughout their childhood. As with any new purchase, they initially and carefully build the specific design for the instructions included ... » read more

Emulating Systems Of Systems


System design is all the craze these days. I have been in notably more discussions recently about how one can verify systems of systems. Does an airplane or a car lend itself to an array of emulators? Are multiple abstractions needed? How can design teams span electrical, mechanical, and thermal—as well as analog and digital—effects? Do companies need to re-organize to deal with system desi... » read more

Impact Of Rising SoC Design Costs On Innovation


If there is one truism in the semiconductor market, it is that rising costs will impact unit demand at some point if they continue long enough. The subject of this blog deals not with device ASPs; but rather with rising SoC design costs, and their effect on the number of designs at the advanced nodes. Even though the mechanism governing each set of numbers is different (device ASPs vs. design c... » read more

Crossing The Chasm: Uniting SoC And Package Verification


Wafer-level packaging enables higher form factor and improved performance compared to traditional SoC designs. However, to ensure an acceptable yield and performance, EDA companies, OSAT companies, and foundries must collaborate to establish consistent and unified automated WLP design and physical verification flows, while introducing minimum disruption to already-existing package design flows.... » read more

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