The Week In Review: Design

New ATPG tool; PCB and AMS; metric-driven verification; interconnect materials; 3D-NoC; open source solutions.



Synopsys unveiled its next-generation ATPG and diagnostics solution, TetraMAX II. According to the company, the tool is an order of magnitude faster than the previous generation, reducing runtime from days to hours, as well as generating 25% fewer patterns. The new tool is also certified for the ISO 26262 automotive functional safety standard. It has been deployed by STMicroelectronics, and Toshiba plans to use it on an upcoming SoC design.

Mentor Graphics expanded its PADS PCB design platform with analog/mixed-signal (AMS) and high-speed analysis products, including a cloud-based circuit exploration/simulation environment and user community, DDR simulation for signal integrity and timing issues, and an electrically-correct design signoff tool.

Aldec beefed up support for Metric-Driven Verification along with other improvements in the areas of Constrained Random Verification and debugging in their latest release of Riviera-PRO. New features include Finite State Machine Coverage, Design Units Viewer, Datasets Window and Covergroup Viewer.

Imec teamed up with Synopsys on an interconnect resistivity model to support the screening and selection of alternative interconnect metals and liner-barrier materials at the 7nm node and beyond, enabling evaluation of interconnect material and process options through simulations in the early stages of technology development.


Synopsys released new USB 2.0 Type-C Controller and PHY IP for IoT edge applications targeting 40nm and 55-nm ultra-low power processes. The USB IP uses 30% lower active power compared to competing solutions and near 0 W of standby power, says the company, and 50% less silicon area. The IP removed 80% of standard USB 2.0 configuration options that are not essential to IoT systems.

Leti demonstrated a new on-chip communications system called 3D-NoC with a homogeneous 3D circuit that is comprised of regular tiles assembled in a 4x4x2 network. The chiplets are fabricated in 28nm FDSOI and integrated on a 65nm CMOS interposer using 1,980 TSVs in a Face2Back configuration.

Open Source

SiFive uncorked the first family of SoC platforms built around the free and open source RISC-V processor. The platforms provide customers with the ability to take the base silicon, create their own silicon enhancements and customizations and then SiFive incorporates those and delivers the end silicon.

If you are concerned about IoT and security, you may be interested in the prpl Foundation’s new light-weight open source hypervisor specifically designed to provide security through separation. That is the goal of prplHypervisor which was designed from the ground up with security in mind for the IoT.


ARM won a deal with Huaxintong Semiconductor Technology, which licensed the ARMv8-A architecture for advanced server chipset technologies in the rapidly expanding Chinese server market. Huaxintong Semiconductor Technology is a joint venture between China’s Guizhou province and a subsidiary of Qualcomm. The area is already home to a data center cluster of more than 2.5 million servers for companies including China Mobile, China Telecom and China Unicom.

Renesas selected Cadence’s Interconnect Workbench (IWB) for performance analysis and verification of their on-chip interconnects, citing a speed increase of up to 50% over its previous methodology.


Cadence’s implementation and signoff tools received certification on the Intel third-generation 10nm tri-gate process for customers of Intel Custom Foundry. Intel utilized a PowerVR GT7200 GPU from Imagination as part of the certification process.