Second in a series on alternative channel materials for post-silicon devices. What are the leading candidates and why are they getting so much attention now?
As discussed in the first article in this series, germanium is one of the leading candidates to succeed silicon as the channel material for advanced transistors, and has been for several years. The fundamental challenges of germanium integration were detailed at length in 2007. Unfortunately, knowing what the issues are does not necessarily lead to a solution.
When a MOSFET transistor turns on, the gate capacitor applies an electric field to the channel, creating an inversion layer. This allows minority carriers (holes in pFETs, electrons in nFETs) to flow between the source and the drain. When the transistor is off there is no capacitance: the energy barriers between the source, drain, and channel prevent current flow. As transistors shrink, the electric field density needed to create the inversion layer increases, and so the gate capacitance must increase. Up to a point, this is accomplished by reducing the thickness of the gate dielectric. As the gate dielectric thickness falls to only a few nanometers, however, quantum mechanical effects allow carriers to tunnel through it, increasing gate leakage and ultimately shorting the transistor.
Silicon transistors already have confronted this issue, which led to the introduction of high-k gate dielectric materials. As the dielectric constant (k) increases, the same capacitance is achieved with a thicker physical layer. Designers can minimize leakage while getting the electrostatic control they need.
The same requirements apply to germanium transistors. In germanium, however, the need to passivate the germanium/dielectric interface introduces additional complexity. In silicon transistors, the presence of a few monolayers of native oxide is a given, and whatever dielectric is used for the gate stack can be deposited onto a stable surface, free of dangling silicon bonds.
A passivated interface is also important for germanium transistors, where interface states can reduce the surface carrier density, but germanium’s native oxides are far less cooperative than SiO2. GeO2 will passivate the surface, but is water-soluble and breaks down to GeO at about 250° C. GeO is unstable, and desorbs at about 450° C. While this behavior makes an atomically clean germanium surface relatively easy to achieve, direct deposition of a metal oxide causes problems, too, as germanium diffuses into the oxide. Moreover, the dielectric tends to grow epitaxially, with lattice mismatch leading to high dislocation densities at the interface.
Early germanium integration schemes depended on thick SiO2 cap layers on top of thick native germanium oxides. These structures provided a stable surface for further dielectric deposition, while preventing breakdown of the oxide. A 2009 review article for the MRS Bulletin concluded that carrier mobility increased as the thickness of these layers did. Unfortunately thick cap layers contribute to the total dielectric thickness and aren’t really an option for sub-10 nm devices, which require an equivalent oxide thickness (EOT) of less than 1 nm.
As John Boland, director of global product marketing at Applied Materials explained, the industry has not yet settled on a single germanium integration scheme. It does appear, however, that even with its flaws, GeO2 may be the best surface passivation layer available, with a metal oxide — typically HfO2 or AlO2 — grown immediately on top of it without breaking vacuum. For example, a joint IBM-MIT project obtained what the researchers claimed was the first germanium-channel MOSFET with sub-1nm EOT by using ozone to passivate the germanium surface, followed by atomic layer deposition of HfO2.
If adopted, this approach will have significant implications for fab operations. While in theory cluster tools always have been able to perform multiple steps in a single tool, in practice fabs have found that dedicating all available chambers to a single process step gives higher overall throughput. If one chamber is shut down, the others can continue to process wafers. If, instead, each chamber is dedicated to a different deposition layer, the loss of one chamber takes the tool offline entirely. Until now, the benefits of increased uptime have outweighed the advantages of atomically clean interfaces between layers, but that equation may be changing.
Other integration schemes being considered deposit a metal oxide directly onto metallic germanium, but then use a post-deposition treatment to form either an oxide or an oxynitride at the interface between the germanium and the dielectric. In work reported at the 2012 IEEE Electron Device Meeting (IEDM, San Francisco) Rui Zhang and colleagues at the University of Tokyo found that both the thickness and the roughness of the resulting interfacial layer affected the carrier mobility of the finished transistor. Increasing the plasma post-oxidation treatment temperature increased the roughness of the germanium/germanium oxide interface, degrading mobility.
Nonetheless, Boland said he expects that Group IV materials, both silicon and germanium, will be with us until well beyond the 10nm technology node. The next step, III-V compound semiconductor channels, poses even more difficult challenges, as the next article in this series will discuss.