Why the throw-it-over-the-wall approach no longer works, and what needs to take its place.
Whether it is the need for sustainable energy, or driving performance while keeping power at bay, or enabling safe and reliable operation of any electronic system, containment of electronic noise — power and signal noise is critical to all of the above. Other factors that impact safe and reliable operation are electromigration (EM), electromagnetic interference (EMI) and mechanical stress enabled by thermal conditions and electro-static discharge (ESD). These requirements call for a design process that enables effective power delivery, suppression of noise and ESD, and a thermally-aware EM methodology across a chip to package to board to sub-system to a system.
In the traditional design process (Figure 2), the chip, package, board and system designs with pre-determined design “margins” are done by totally different teams, often from two or more companies. System designers could patch up any misalignment for a specific application with decaps, suitable cooling options and extra compensation in power and ground planning. But evolving markets are putting this traditional approach to planning under severe pressure.
Cost-sensitive IoT edge devices cannot afford to use expensive options like multiple decaps, bulk caps for noise-suppressions, big heatsinks and multi-layer boards. In addition, automotive, industrial, medical and many other applications now need to deliver unusually high reliability. Yet these design still need to provide sufficient margin against noise to be able to operate securely.
Meanwhile in the cloud, massive multiprocessors are densely packed on boards with memories and other components, and these boards are densely packed in racks. Since servers are typically always-on, reliability risks from hotpots or thermal runaway are increased. Gating processor speed to avoid over-heating compromises performance, yet cooling contributes significantly to datacenter costs. And while running systems at lower voltage reduces thermal risks, that mode of operation also reduces performance and greatly increases sensitivity to noise.
These problems become even more urgent as interest grows in advanced packaging techniques—2.5D, 3D and wafer-level. At these levels of integration, given very close proximity between package connectivity and die, issues in EM, ESD, EMI and even mechanical strain, normally managed separately at board chip levels, become a direct concern across the extended package.
These competing objectives are forcing changes in design objectives from the traditional, “throw-it-over-the-wall” model to a Chip-Package-System (CPS) co-design and co-analysis flow, to optimize for power integrity and thermal management, and for advanced packaging in EM/ESD/EMI and mechanical integrity.
The task of optimizing a power distribution network (PDN) for power integrity is a good example of why analysis needs to span a chip, package and system. Due to widely-differing impedances at each of these levels, response times differ dramatically. Further the current signature in the PDN, which drives power noise, is a function of slew rate and is also closely related to frequency response. In each case, these factors couple across frequency domains so independent decoupled analysis of each domain is inevitably inaccurate.
In an upcoming webinar, ANSYS will illustrate how it is enabling the ‘Chip-Package-System’ analysis. Workflows and methodologies between players will be described with examples.