Negative-Tone Photosensitive Polymeric Bonding Material To Enable Room Temperature Prebond For Cu/Polymer Hybrid Bonding


An evaluation of a negative-tone i-line photosensitive polymeric bonding material for achieving prebonding in Cu/polymer hybrid bonding at low temperatures via the Cu damascene process. The polymeric material has a Tg≤100∘C ; Young’s modulus of 99 MPa, the dielectric constant of 2.6, and dissipation factor of 0.0016 at 10 GHz. Shear tests revealed a bond shear strength of over 10 MPa when... » read more

Why Using Commercial Chiplets Is So Difficult


Experts at the Table: Semiconductor Engineering sat down to discuss use cases and challenges for commercial chiplets with Saif Alam, vice president of engineering at Movellus; Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software; Mark Kuemerle, vice president of technology at Marvell; and Craig Bishop, CTO at Deca Technologies. What follows are excerpts... » read more

AI Process Control Platform Enabling Next Generation Technology, Part 2


As feature dimensions in semiconductors continue to shrink and worldwide demand continues to expand, semiconductor equipment manufacturers need innovative ways to compete and deliver. The Tignis PAICe Maker physics-driven AI computational modeling platform accelerates leading-edge semiconductor manufacturing—from equipment R&D to reliable high-yield chip fabrication capability. Tignis sup... » read more

Survey: 2023 eBeam Initiative Luminaries Survey Results


Luminaries are confident in high-NA EUV and curvilinear masks 12th Annual Luminaries Survey — July 2023 • Luminaries remain confident in broad High-NA EUV adoption by 2028 • Confidence doubled in leading-edge mask shops handling curvilinear mask demand • Curvilinear masks aren’t just for EUV • Luminaries are more confident about 2023 mask revenues than SEMI Click here to rea... » read more

Blog Review: October 18


Siemens' Stephen Chavez suggests including analog mixed signal analysis and board level parasitics within the design process from the earliest electrical design stage and throughout final release of the PCB design. Synopsys’ Filip Thoen, Leonard Drucker, and Vivek Prasad highlight how the complexities and interdependencies of multi-die systems create new challenges for software bring-up, a... » read more

Verifying A RISC-V Processor


Verifying an SoC is very different than verifying a processor due to the huge state space in the processor. In addition to the tools needed for an SoC, additional tools are required for a step and compare environment. Larry Lapides, vice president at Imperas, talks about the need to verify asynchronous events like interrupts, how to compare a reference model to RTL, and the need for both hardwa... » read more

EDA Revenue Up Again


The EDA industry reached $3.963 billion in revenue in Q2, boosted by a 17.6% increase in computer-aided engineering and a 17.2% increase in IP physical design and verification, according to a just-released ESD Alliance Electronic Market Data report. The overall growth was offset by an accounting change in the IP business, which resulted in a 11.6% decline to $1.255 billion, as well as some w... » read more

Chip Industry’s Technical Paper Roundup: October 17


New technical papers added to Semiconductor Engineering’s library this week. [table id=155 /] More Reading Technical Paper Library home » read more

Research Bits: October 17


High-entropy multielement ink semiconductors Researchers from Lawrence Berkeley National Laboratory and UC Berkeley developed a high-entropy semiconducting material called ‘multielement ink’ that can be processed at low-temperature or room temperature. “The traditional way of making semiconductor devices is energy-intensive and one of the major sources of carbon emissions,” said Pei... » read more

LLMs For Hardware Design Verification


A technical paper titled “LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation” was published by researchers at University of Cambridge, lowRISC, and Imperial College London. Abstract: "Test stimuli generation has been a crucial but labor-intensive task in hardware design verification. In this paper, we revolutionize this process by harnessing the power of large langua... » read more

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