EDA, IP Revenue Way Up
By Ed Sperling - 17 Oct, 2022 - Comments: 0

EDA and semiconductor IP sales grew 17.5% to $3.75 billion in Q2, the highest growth in more than a decade, fueled by more complex designs and the need for advanced design and verification tools. Demand for nearly every segment tracked in SEMI's Electronic Design Market Data (EDMD) report was up, including services, which grew 23.2% in Q2 — the most recent statistics available in. That cou... » read more

HBM3 In The Data Center
By Ed Sperling - 17 Oct, 2022 - Comments: 0

Frank Ferro, senior director of product management at Rambus, talks about the forthcoming HBM3 standard, why this is so essential for AI chips and where the bottlenecks are today, what kinds of challenges are involved in working with this memory, and what impact chiplets and near-memory compute will have on HBM and bandwidth.     » read more

What Is The Definition Of Design For Context?
By Don Dingee - 17 Oct, 2022 - Comments: 0

EDA industry pundits and bloggers are latching onto a new term: design for context. So far, it has eluded a crisp yet complete definition. It's one of those ideas that if you ask ten people about it, you get ten different answers – some better than others. Ed Sperling wryly observed this in his recent panel discussions about the topic: "Even my questions are getting longer." When Keysight lis... » read more

Complex Tradeoffs In Inferencing Chips
By John Koon - 17 Oct, 2022 - Comments: 0

Designing AI/ML inferencing chips is emerging as a huge challenge due to the variety of applications and the highly specific power and performance needs for each of them. Put simply, one size does not fit all, and not all applications can afford a custom design. For example, in retail store tracking, it's acceptable to have a 5% or 10% margin of error for customers passing by a certain aisle... » read more

A Security Maturity Model For Hardware Development
By Jim Robinson - 17 Oct, 2022 - Comments: 0

With systems only growing more sophisticated, the potential for new semiconductor vulnerabilities continues to rise. Consumers and hardware partners are counting on organizations meeting their due diligence obligations to ensure security sensitive design assets are secure when products are shipped. This is an iterative process, so a security maturity model is a critical element in getting it ri... » read more

Hardware Platform Based on 2D Memtransistors
By Technical Paper Link - 15 Oct, 2022 - Comments: 0

A new technical paper titled "Hardware implementation of Bayesian network based on two-dimensional memtransistors" from researchers at Penn State University. "In this work, we demonstrate hardware implementation of a BN [Bayesian networks] using a monolithic memtransistor technology based on two-dimensional (2D) semiconductors such as monolayer MoS2. First, we experimentally demonstrate a lo... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 14 Oct, 2022 - Comments: 0

The United States imposed further export controls aimed at preventing foreign firms from selling advanced chips to China or supplying Chinese firms with semiconductor processing tools. Under new regulations, companies looking to supply Chinese chipmakers with advanced manufacturing equipment (<14nm) must first obtain a license from the U.S. Department of Commerce. Officials noted that they h... » read more

Week In Review: Auto, Security, Pervasive Computing
By Marie C. Baca - 14 Oct, 2022 - Comments: 0

Automotive, Mobility Hyundai announced all of its vehicles will be software-defined vehicles (SDVs) by 2025. The company said all newly launched Hyundai vehicles will be able to receive over-the-air software updates next year, and that it expects to register 20 million vehicles to its Connected Car Services system by 2025. Hyundai also said it will invest the equivalent of more than $12 billio... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Oct, 2022 - Comments: 0

Cadence unveiled a new environment to automate and accelerate the complete design closure cycle from signoff optimization through routing, static timing analysis (STA), and extraction. The Certus Closure Solution allows concurrent, full-chip optimization through a massively parallel and distributed architecture and engine shared with Cadence’s Innovus Implementation System and the Tempus Timi... » read more

Thermal Scanning Probe Lithography
By Technical Paper Link - 13 Oct, 2022 - Comments: 0

A new technical paper titled "Edge-Contact MoS2 Transistors Fabricated Using Thermal Scanning Probe Lithography" was published by researchers at École Polytechnique Fédérale de Lausanne (EPFL). "Thermal scanning probe lithography (t-SPL) is a gentle alternative to the typically used electron beam lithography to fabricate these devices avoiding the use of electrons, which are well known to... » read more

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