Pathfinding By Process Window Modeling
By Coventor - 19 Oct, 2022 - Comments: 0

In advanced DRAM, capacitors with closely packed patterning are designed to increase cell density. Thus, advanced patterning schemes, such as multiple litho-etch, SADP and SAQP processes may be needed. In this paper, we systematically evaluate a DRAM capacitor hole formation process that includes SADP and SAQP patterning, using virtual fabrication and statistical analysis in SEMulator3D®. The ... » read more

Memory-Computation Decoupling Execution To Achieve Ideal All-Bank PIM Performance
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling" was published by researchers at Korea University. "This paper proposed the memory-computation decoupled PIM architecture to provide the performance comparable to the all-bank PIM while preserving the standard DRAM interface, i.e., DRAM commands, powe... » read more

Nonvolatile ECRAM With A Short-Circuit Retention Time Several Orders of Magnitude Higher Than Previously Shown
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Nonvolatile Electrochemical Random-Access Memory Under Short Circuit" was published by researchers at University of Michigan and Sandia National Laboratories. Abstract "Electrochemical random-access memory (ECRAM) is a recently developed and highly promising analog resistive memory element for in-memory computing. One longstanding challenge of ECRAM is attainin... » read more

Locking-Based Design-For-Security Methodology To Prevent Piracy of RF transceiver ICs
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Anti-Piracy Design of RF Transceivers" was published by researchers at Sorbonne Universite (France). Abstract: "We present a locking-based design-for-security methodology to prevent piracy of RF transceiver integrated circuits. The solution is called SyncLock as it locks the synchronization of the transmitter with the receiver. If a key other than the secret ... » read more

On-chip 2D/3D Photonics Integration Solution Using Deposited Polycrystalline Silicon for Optical Interconnects Applications
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Polycrystalline silicon PhC cavities for CMOS on-chip integration" was published by researchers at Tyndall National Institute, Munster Technological University, and Université Grenoble Alpes, CEA, LETI. "In this work, we present an on-chip 2D and 3D photonics integration solution compatible with Front End of Line integration (FEOL) using deposited polycrystalli... » read more

Simulating the Groundstate and Dynamics of Quantum Critical Systems
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Simulating groundstate and dynamical quantum phase transitions on a superconducting quantum computer" was published by researchers at London Centre for Nanotechnology, University College London, University of Massachusetts, and Google Quantum AI. Abstract (partial) "The phenomena of quantum criticality underlie many novel collective phenomena found in condensed... » read more

Wafer Scale Tool To Transfer Graphene
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Assessment of wafer-level transfer techniques of graphene with respect to semiconductor industry requirements" was published by researchers at RWTH Aachen University, AMO GmbH, Infineon Technologies, Protemics GmbH, and Advantest Europe. Abstract (partial): "Graphene is a promising candidate for future electronic applications. Manufacturing graphene-based elect... » read more

Why Changes In Computing Are Driving Changes In Photomasks
By Ed Sperling - 18 Oct, 2022 - Comments: 0

Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about massive improvements in computation based upon increased density on chips, and why printing Manhattan shapes on a photomask are no longer sufficient to print high-performance devices with predictable reliability every time. He explains why a discontinuity in EDA physical design has opened the door for printing curvilinear shap... » read more

Chip Industry’s Technical Paper Roundup: Oct 18
By Linda Christensen - 18 Oct, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=57 /] » read more

Research Bits: Oct. 18
By Jesse Allen - 18 Oct, 2022 - Comments: 0

Modular AI chip Engineers at the Massachusetts Institute of Technology (MIT), Harvard University, Stanford University, Lawrence Berkeley National Laboratory, Korea Institute of Science and Technology, and Tsinghua University created a modular approach to building stackable, reconfigurable AI chips. The design comprises alternating layers of sensing and processing elements, along with LEDs t... » read more

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