MIPI Drives Performance For Next-Generation Displays
By Rambus - 07 Jul, 2021 - Comments: 0

MIPI Alliance technology has helped enable the dramatic growth of the mobile phone market. The function and capabilities of MIPI interface solutions have grown dramatically as well. MIPI DSI-2 has become the leading display interface across a growing range of products including smartphones, AR/VR, IoT appliances, and ADAS/autonomous vehicles. As the application space has expanded, so too have t... » read more

When Failure Is Not An Option: Improving Medical Device Reliability
By Ansys - 07 Jul, 2021 - Comments: 0

Medical electronics are expected to operate safely over extended periods of time to provide monitoring, therapeutic or life-sustaining functions for patients. Without built-in reliability, these devices could experience failures or malfunctions that greatly increase the possibility of infection or death. In the movie Apollo 13, NASA’s Gene Kranz (played by actor Ed Harris) made the phrase “... » read more

Dynamic Fault Injection Into Digital Twins Of Safety-Critical Systems
By Fraunhofer IIS/EAS - 07 Jul, 2021 - Comments: 0

In this work we present a technology for dynamically introducing fault structures into digital twins without the need to change the virtual prototype model. The injection is done at the beginning of a simulation by dynamically rewiring the involved netlists. During the simulation on a real-time platform, faults can be activated or deactivated triggered by sequences, statistical effects or by ev... » read more

Startup Funding: June 2021
By Jesse Allen - 07 Jul, 2021 - Comments: 0

June was the month of mega-rounds for autonomous driving companies, with three pulling in well over $100M. All three are based in China, but their products range from chips to full robotaxi services. Also in the automotive space, an EV battery manufacturer raised over $2B, a solid-state lidar developer drew $300M — and those are just the largest rounds. Plus, new HPC architectures, GAA metrol... » read more

Blog Review: July 7
By Jesse Allen - 07 Jul, 2021 - Comments: 0

Cadence's Sangeeta Soni provides a primer on the PIPE SerDes architecture and some of the changes that can introduce verification challenges for SerDes compliant PHY and MAC devices. Siemens EDA's Chris Spear demystifies the $cast() method in SystemVerilog, which checks values at runtime rather than compile time, and gives some examples of when it is useful. Synopsys' Chris Clark warns th... » read more

Cell Library Verification Using Symbolic Simulation
By Hari Sathianathan - 07 Jul, 2021 - Comments: 0

Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models describing the cell functionality, schematic derived transistor level netlists, place and route views, physical layout views, post-layout extracted netlists as well as characterized timing and power m... » read more

Optimize Physical Verification Cost Of Ownership With Elastic CPU Management
By Synopsys - 07 Jul, 2021 - Comments: 0

For physical verification, advanced process technology nodes create implementation challenges. Design sizes have gotten larger and required rules from foundries have become more numerous in count (thousands) and more complex (hundreds of discrete steps). For these reasons, physical verification tools have been able to span these jobs not only across multiple CPUs on a single physical compute ho... » read more

5G Chips Add Test Challenges
By Bryon Moyer - 06 Jul, 2021 - Comments: 1

The advent of chips supporting millimeter-wave (mmWave) 5G signals is creating a new set of design and testing challenges. Effects that could be ignored at lower frequencies are now important. Performing high-volume test of RF chips will require much more from automated test equipment (ATE) than is required for chips operating below 6 GHz. “MmWave design is a pretty old thing,” said Y... » read more

Packetized Scan Test Delivery
By Geir Eide - 06 Jul, 2021 - Comments: 0

The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To address these challenges, we now have the option of implementing a packetized data network for scan test that moves the scan data through the SoC much more efficiently than the traditional pin-... » read more

Achieving CDC Signoff On Multi Billion Gate Designs With Hierarchical CDC Flow
By Synopsys - 06 Jul, 2021 - Comments: 0

For the last few decades, the System-on-Chip (SoC) design size has dramatically increased and more complexity has been introduced to deliver the desired functionality. A typical SoC can have many complex IPs operating at different clock frequencies, which can stress the verification cycle. Generally, design and verification teams are spending an increasing amount of time to ensure that the SoC ... » read more

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