Architectural Considerations For AI
By Brian Bailey - 24 Jun, 2021 - Comments: 2

Custom chips, labeled as artificial intelligence (AI) or machine learning (ML), are appearing on a weekly basis, each claiming to be 10X faster than existing devices or consume 1/10 the power. Whether that is enough to dethrone existing architectures, such as GPUs and FPGAs, or whether they will survive alongside those architectures isn't clear yet. The problem, or the opportunity, is that t... » read more

Early Simulation Of Multi-Cycle Paths And False Paths
By Taruna Reddy - 24 Jun, 2021 - Comments: 0

Designing with synchronous clocks avoids metastability issues on clock domain crossings, but it presents its own challenges when multi-cycle and false paths are involved. A multi-cycle path (MCP) occurs when a logical function requires more than one clock cycle to produce a final, stable result. The designer must ensure that the destination register does not clock until the result is ready. Thi... » read more

Smart Home Device Communication In The Era Of Hyperconnectivity
By Frank Schirrmeister - 24 Jun, 2021 - Comments: 0

In our increasingly hyperconnected world, a fascinating area to watch is what I would call "the last 100 feet, give or take." There are many standards like Wi-Fi, Bluetooth, Zigbee, or Thread used for IoT device connectivity. There are very active discussions about how our smart devices should be allowed to talk to other resources, like our neighbor's Wi-Fi. In the IoT's municipal and industria... » read more

CEO Outlook: More Data, More Integration, Same Deadlines
By Ed Sperling - 24 Jun, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

An Introduction To Domain-Specific Accelerators
By Roddy Urquhart - 24 Jun, 2021 - Comments: 0

After 50 years, Moore’s Law, Dennard Scaling, and Amdahl’s Law are failing. The semiconductor industry much change, and processor paradigms must change with it. So what exactly are domain-specific accelerators and why are they so important in light of the failure of these semiconductor scaling laws? » read more

Verilog HDL And Its Ancestors And Descendants
By Imperas - 23 Jun, 2021 - Comments: 0

This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog has completely revolu- tionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. For large-scale digital logic design, previous schematic-based techniq... » read more

Using A System Technology Co-Optimization (STCO) Approach For 2.5/3D Heterogeneous Semiconductor Integration
By Siemens EDA - 23 Jun, 2021 - Comments: 0

With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the system technology co-optimization (STCO) concept, where a SoC type system is disaggregated, or partitioned, into smaller modules (also known as chiplets) that can be asynchrono... » read more

Blog Review: June 23
By Jesse Allen - 23 Jun, 2021 - Comments: 0

Synopsys' Manuel Mota shows how splitting SoCs into smaller dies for advanced packaging and using die-to-die interfaces to enable high bandwidth, low latency, and low power connectivity can benefit hyperscale data centers. Siemens EDA's Chris Spear explains the relationship between classes and objects in SystemVerilog with a handy visualization and notes the difference between SystemVerilog ... » read more

IP Solutions For A Data-Centric World
By Cadence - 23 Jun, 2021 - Comments: 0

We’re in an era of sizeable growth in data and compute demand, along with increasing global data traffic. As a result, high-performance computing, data communications, networking, and storage systems are taking center stage in many application areas, driven by newer applications such as analytics, artificial intelligence (AI), genomics, and simulation-intensive workloads. Power efficiency, hi... » read more

Debugging Point-to-Point Resistance Using Contribution By Layer In IC Validator PERC
By Synopsys - 23 Jun, 2021 - Comments: 0

PERC Point-to-point resistance (P2P resistance) functionality is a crucial EDA technology to enable complex P2P effective resistance measurement along ESD paths in automation for foundry qualified ESD/Latch-up checker or in-house custom checker. This technology is applied to the entire chip, block, and IP designs on cell or transistor level layout database. Since the ESD path count could grow t... » read more

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