category: Blogs – LPHP

category: Auto, Security & Edge AI

Extending Power Analysis To The Emulation of Complex SoCs
By Jim Kenney - 11 Sep, 2014 - Comments: 0

Using hardware emulation to estimate SoC power consumption delivers significant value. Emulators are capable of long runs on large designs, making it practical to emulate an RTOS boot sequence or graphics processing of multiple frames. Estimating power consumption of these advanced functions executing across the complete SoC provides valuable insight into the chip’s power draw and its impact ... » read more

Collaboration Accelerates Moore’s Law
By Joe Gullo - 11 Sep, 2014 - Comments: 0

Moore's Law dictates that the number of transistors in dense, integrated circuits will double approximately every two years. Maintaining this pace of scaling, however, has become increasingly difficult given the ever-increasing complexity inherent with new chip starts. Additionally, the cost of using leading-edge process technology is prohibitively expensive. As a result, collaboration amon... » read more

Server Memory: Should We Be Concerned About The Power?
By Loren Shalinsky - 07 Aug, 2014 - Comments: 0

After my last blog post, Server Memory: What Drives its Growth, I had a couple of people ask me, “If server memory has increased by so much in the last four years, what effect has that had on the server memory subsystem power consumption?” It’s a good question. In last month’s blog, I calculated that the maximum memory per CPU has increased from 18GB (2010, highest-end Nehalem 45nm C... » read more

Enabling The Next Mobile Computing Revolution
By Brian Jeff - 07 Aug, 2014 - Comments: 0

We’ve come a long way Just think about the ‘mobile computing’ revolution over the last five years – the compute tasks we routinely handle on our mobile phonesdaily, equal those that were only possible to execute using laptops and desktops several years ago. With a direct and uninterrupted power supply from the wall, laptopsand desktops require fan-assisted cooling, a... » read more

Power Reduction Techniques
By Mary Ann White - 07 Aug, 2014 - Comments: 0

As 16nm and 14nm finFET process nodes come into production toward the end of this year, the performance (up to 30% vs. 28nm planar CMOS), power (~30%) and area (up to ~50%) benefits have been well documented. The same can be said for the 28nm FD-SOI process as it gains more traction in the marketplace touting similar performance and power improvements as those for FinFET when compared against i... » read more

IP/SoC Verification With Assertions
By Larry Vivolo - 07 Aug, 2014 - Comments: 1

There's been a lot of excitement here in Silicon Valley these past weeks with the opening of the new 49ers stadium. I've always found it amazing to see how so many complex, fundamentally different technologies — mechanical, electrical, HVAC, plumbing, audiovisual, food catering, etc. — can be put together to create a functioning ballpark. It all but takes a mastermind to bring all these eng... » read more

Partitioning The Problem
By Ann Mutschler - 07 Aug, 2014 - Comments: 0

Whether it is solving a very tricky equation, cleaning out your hard drive or creating a power-aware test plan for your SoC, it helps to break the problem down into smaller pieces. There is so much involved with writing a test plan these days, let alone one that is power aware that I wasn’t all that surprised to hear from Erich Marschner, verification architect at Mentor Graphics that in t... » read more

Creating A Strategy For Power Reduction In ICs
By Rob Eccles - 07 Aug, 2014 - Comments: 0

In last month’s blog, various power saving techniques were presented. These different techniques fit into three categories: gross (or coarse-grain) design, fine-grain design, and fine-grain process. In this blog, different techniques will be compared. By understanding the different techniques, it will become clear which ones to use in your design. Fine-grain process techniques For ... » read more

Changing The Meaning Of Sign-Off
By Muhammad Zakir - 07 Aug, 2014 - Comments: 0

Chip development teams are faced with an ever-increasing number of power integrity and reliability challenges these days, especially as designs adopt FinFET technology. Even those with the most thorough sign-off checks often encounter unexpected surprises that quickly turn into tape-out hurdles, or worse yet, extensive re-design. The best way to avoid this scenario and ensure a smoother sign-of... » read more

If It Ain’t Broke, Start Fixing It Right Away
By Brian Fuller - 07 Aug, 2014 - Comments: 0

"If it ain't broke don't fix it." It’s a line that can lull businesses into fatal complacency. It lies at the heart of Harvard Professor Clayton Christensen's innovator's dilemma writings: The products or services driving a successful business "ain't broke," but they usually prevent companies from anticipating or responding to disruptive innovation outside their walls. Our electronics ind... » read more

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