category: Blogs – LPHP

category: Auto, Security & Edge AI

Memory VIP
By Neill Mullinger - 09 Oct, 2014 - Comments: 0

As the consumer market, and the mobile segment in particular, continues to demand more features and more performance in their gadgets, the designer community is confronted with myriad challenges of delivering on those demands – not the least of which is verifying compliance of ever-evolving protocols that enable the connection of everything within the system on chip (SoC), and the connection ... » read more

Taking The Mystery Out Of IP, SoC And Automotive System Debug
By Larry Vivolo - 09 Oct, 2014 - Comments: 0

I recently had to take my car to the dealership because the gas-saving "auto-shut-off-while-stopped" feature wasn't working. The dealer explained that the reason it took two days to debug was because it "touched on many systems" in the car. In the end, they realized the battery wasn't fully charged and blamed it on my short 10-mile commute. Whether that was an honest answer or an example of ... » read more

Brain-Inspired Power
By Barry Pangrle - 01 Oct, 2014 - Comments: 1

“Let’s be clear: we have not built the brain, or any brain. We have built a computer that is inspired by the brain. The inputs to and outputs of this computer are spikes. Functionally, it transforms a spatio-temporal stream of input spikes into a spatio-temporal stream of output spikes.” — Dharmendra Modha, IBM Fellow It’s generally a well-accepted principle that the biggest savings... » read more

How To Reduce Implementation Headaches In FinFET Processes
By Leah Schuth - 11 Sep, 2014 - Comments: 0

In this era of compressed market windows and shrinking or changing technology, today’s engineers are always looking for ways to improve their overall product performance, power and area (PPA), while also decreasing their SoC design effort. The goal is to ease time-consuming and labor-intensive implementation tasks that will yield a reduction in design time, without sacrificing accuracy and op... » read more

Can RTL Clock Power Be Accurate Enough For Sub-20nm Multi-GHz Designs?
By Preeti Gupta - 11 Sep, 2014 - Comments: 0

The Register Transfer Language (RTL) has increasingly been adopted to enable early and high-impact power decisions. As a cycle-accurate hardware abstraction, RTL is expected to deliver reasonable power accuracy. Clocks are particularly important to analyze and optimize for power. They switch the most and drive the highest loads. Clock gating is an effective power reduction technique that shuts ... » read more

Datacenter Power Is Different
By Ann Mutschler - 11 Sep, 2014 - Comments: 1

With much focus on super low power devices for handhelds and IoT applications, I’m also interested in what’s happening at the seeming other end of the spectrum, in the datacenter. Atrenta CTO Bernard Murphy rightly pointed out that when it comes to power reduction techniques, datacenter power is a different story. He reminded that at a unit-level, a lot has already been done or is underw... » read more

Low Power Design: RTL Power Analysis
By Anand Iyer - 11 Sep, 2014 - Comments: 0

In last month’s blog, we discussed and compared various power techniques. A quick recap of these power techniques is shown in figure 1. Selecting between them is often quite challenging. These techniques need to be selected during RTL design. At the RTL, designers need a power analysis solution that guides them to the right techniques for their design. In this month’s blog, we will review t... » read more

Where Is Gene Roddenberry When You Need Him?
By Brian Fuller - 11 Sep, 2014 - Comments: 1

As we chatted the other day, my colleague Scott Lewis said something so deceptively simple that it made us stop in our tracks. “We need another Gene Roddenberry,” he said. The Star Trek creator in the 1960s introduced the world to an array of futuristic technologies (the tricorder, wireless ear sets and so on) that in effect became our collective electronics product roadmap. We have m... » read more

Advances In Power Management For Physical IP In 28nm And FinFET Process Nodes
By Navraj Nandra - 11 Sep, 2014 - Comments: 0

Engineering techniques to reduce power consumption by lowering the supply voltage and slowing the clock speed have reached practical limits of the semiconductor technologies. Newer solutions, which not only reduce power but also actively manage the power during the course of the SoC (system on chip) activity, are emerging. This article describes these innovations from the foundation intellectua... » read more

Manufacturing Test Robustness
By Kiran Vittal - 11 Sep, 2014 - Comments: 0

The recent 6.0 earthquake near Napa California caused close to $50 million in damages to the wineries and property in the region. The San Francisco bay area is accustomed to earthquakes and hence structural engineers design buildings to bear high intensity earthquakes amongst other natural disasters. The damage to property would have been much higher if not due to the strict guidelines followed... » read more

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