category: Blogs – LPHP

category: Auto, Security & Edge AI

Efficient Hierarchical Verification For Low Power Designs
By Susantha Wijesekara - 17 Jan, 2019 - Comments: 0

By Susantha Wijesekara and Himanshu Bhatt Growing design sizes, low power (LP) complexity and the need for early stage verification is making designers adopt hierarchical verification flows. Traditionally for hierarchical verification, designers use a black box, liberty model based hierarchical flow, timing model (ETM) flow or stub/glass box flows that offer various degrees of trade-offs for... » read more

Trends In FPGA Effectiveness: The 2018 Wilson Research Group Functional Verification Study
By Harry Foster - 17 Jan, 2019 - Comments: 0

We all know that knowledge is power. The adage holds true even in the prosaic case of making informed decisions backed by good data. Our hope and motivation in conducting the worldwide Wilson Research Group Functional Verification Study is to provide our community the information needed to make the best methodology and tool choices for their business and design goals. As well, we at Mentor, ... » read more

Cutting The Cord: How Edge Intelligence Is Enabling The IoT To Go Where Cloud Can’t
By Chris Shore - 17 Jan, 2019 - Comments: 3

In a world where data’s time to value or irrelevancy may be measured in milliseconds, the latency introduced in transferring data to the cloud threatens to undermine many of the Internet of Things’ most compelling use cases. Think of data as the fuel that powers our new decision-making engines – fail to get the fuel to the engines fast enough and the engine splutters and dies. Meanwhil... » read more

PCIe 4.0 Hangs In, PCIe 5.0 Coming On Strong
By Mondeep Thiara - 17 Jan, 2019 - Comments: 0

First introduced in 2003 as a universal serial chip-to-chip interface running at 2.5 Gbps, PCI Express (Peripheral Component Interconnect Express), also known as PCIe, has advanced several revisions with significant improvements to performance and other features with each new generation. Through broad support, backwards compatibility, and a consistent cadence of upgrades that doubled lane sp... » read more

How to Make Sure IP will Float in the Rough SoC Sea
By Magdy Abadir - 19 Dec, 2018 - Comments: 0

Today a typical SoC includes hundreds of instances of IP modules both digital and analog. These IPs are typically verified individually by the vendors. The burden of guaranteeing functionality when placed in the midst of a monster SoC is typically left to the SoC owner. With increasing frequencies, tighter margins, denser integrated circuits, new devices and materials, the task of verifying So... » read more

How to nail functional safety in your next design
By Neil Stroud - 14 Dec, 2018 - Comments: 0

As the automotive industry accelerates innovation toward fully autonomous vehicles, one of the underlying values of this effort will be safer roadways. Nine in 10 vehicle accidents are caused by human error. Work underway, and future innovation in autonomous and semi-autonomous vehicles, should shrink driving fatalities by tens of thousands in much the same way that the introduction of seat bel... » read more

Efficient Low Power Verification & Debug Methodology Using Power-Aware Simulation
By Himanshu Bhatt - 13 Dec, 2018 - Comments: 1

By Himanshu Bhatt and Shreedhar Ramachandra Isolation, retention, and power switches are some of the important functionalities of power-aware designs that use some of the common low power techniques (e.g.) power shutoff, multi-voltage and advanced techniques (e.g.) DVFS, Low VDD standby, and biasing. The strategies for isolation, retention, and level shifter are specified in the power forma... » read more

A New Approach To Resistance Extraction For Unconventional Geometries
By Hossam Sarhan - 13 Dec, 2018 - Comments: 0

Unconventional metal structures have begun popping up in integrated circuits (ICs) with increasing regularity, for a number of reasons. The growing demand for integrated cameras and image recognition capabilities has fueled the need for components such as high-quality CMOS image sensors with low noise, high dynamic range, and low power. Technology scaling has also contributed to an increase in ... » read more

Taking Steps Toward Hybrid Memory
By Ken Wright - 13 Dec, 2018 - Comments: 0

What is the memory subsystem of the future, and how do we get there? Since our Hybrid Memory research program began, Rambus Labs and its industry partners and collaborators have made significant progress under the banner of OpenPOWER and OpenCAPI Foundations, an open development community based on the POWER microprocessor (mP) architecture. Rambus Labs is using the Wistron POWER9 systems’ Ope... » read more

Containing Design Complexity With POP IP
By Kelvin Low - 16 Nov, 2018 - Comments: 0

About 25 years ago, Carver Mead, one of the pioneers of VLSI design, told a technical audience then grappling with the complexities of quarter-micron design that he could see an evolutionary path to about 130nm, but after that point, the picture blurred. Flash forward to the present and we’re manufacturing SoCs at 7nm, and the output is truly amazing devices powering applications we and Me... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy