Rethinking The Role Of CPUs In AI: A Practical RAG Implementation


In many enterprise environments, engineers and technical staff need to find information quickly. They search internal documents such as hardware specifications, project manuals, and technical notes. These materials are often scattered, making traditional search inefficient. These documents are often confidential or proprietary. This constraint prevents these documents from being processed by... » read more

Limited by Power


AI is seen as a massive computation problem, but that is not the case, at least with the way that the problem is structured today. It is a data movement problem. This not only limits performance but represents most of the energy consumption. In addition, the industry spends most of its time and effort making small improvements that optimize aspects of the existing architecture, when what is ... » read more

Harness Simulation To Connect To Industry 5.0


Industry 5.0 represents a significant evolution in industrial processes, focusing on integrating human-centric approaches with advanced technologies. Unlike Industry 4.0, which emphasizes automation and digitalization, Industry 5.0 prioritizes collaboration between humans and technology. This approach broadens the scope of industrial advancements to include societal contributions alongside prod... » read more

AI Buildout Makes HPC Simulation More Challenging


Simulations of semiconductors and systems are becoming bigger, more complex, and increasingly necessary, mirroring everything that is happening to the hardware itself — particularly in AI data centers. The move beyond monolithic chips to multi-die assemblies now requires solving some thorny multi-physics challenges, such as thermal and power delivery, which are increasingly difficult to mo... » read more

Evaluating A PDN Based On Jitter


Power distribution networks (PDN) must supply current fast enough to meet the switching needs of high-performance integrated circuits. As the voltage regulator module can only supply current up to a limited frequency range, decoupling capacitors are added to the PDN to provide a low impedance path for current to flow to the IC. This paper describes a simulation methodology to automatically meas... » read more

Streamlining DO-254 Compliance: The Power Of Automated Clock-Domain Crossing Verification


In the realm of safety-critical electronic hardware, particularly those governed by DO-254 compliance directives, ensuring design integrity is paramount. One of the most insidious challenges designers face is clock-domain crossing (CDC) violations. When data moves between asynchronous clock domains, it can lead to metastability issues, causing unpredictable behavior, data loss or corruption, an... » read more

Chiplets Vs. Soft IP: Different In Almost Every Way


Chiplets serve a similar function as the soft IP widely used in chips today, but the similarities end there. While both can speed time to market and enable design teams to focus limited resources where they can best be applied, the implementation, manufacturing, test, and long-term business requirements wrought by a chiplet marketplace would be very different. Soft IP (also known as RTL IP) ... » read more

Arm Performance Cookbook: Your Guide to Optimal Design and Verification (EBook)


The Performance Cookbook for Arm is your essential resource for mastering the complexities of system-level performance, architecture exploration, and SoC verification. Why Download the Performance Cookbook? In-Depth Exploration - Dive into the evolution of Arm compute subsystem architectures, with detailed coverage on how critical components interact to deliver optimal performance be... » read more

Next Generation AI: Transitioning Inference from the Cloud to the Edge


Deploying AI inference at the edge—on smartphones, appliances, industrial devices, and vehicles—promises faster, private, and energy-efficient intelligence. Expedera’s packet-based NPU architecture delivers up to 90% utilization and dramatic reductions in memory movement compared to conventional approaches, enabling next-generation real-time AI capabilities. This white paper examines tech... » read more

Designing for 448G: Modulation, DSP, and Channel Trade-offs in High-Speed SerDes


Discover practical solutions and engineering insights for deploying 448G SerDes in AI and HPC cluster networks. In this white paper, you’ll learn: The impact of retimed vs. unretimed host architectures on signal integrity and power Key trade-offs between PAM4 and PAM6 modulation Channel design simulations and DSP implications using real-world 448G topologies Equalization stra... » read more

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