category: Manufacturing, Packaging and Materials

category: Auto, Security & Edge AI

Virtual Twins: Layers Of Challenges
By Ed Sperling - 15 Sep, 2025 - Comments: 0

Virtual twins can provide deep insights into complex systems at any point in time, but creating them requires integrating a stack of abstractions that don't naturally go together. One abstraction may be mechanical, another electrical, and the data used to create those abstraction layers needs to be fused together logically and updated over time. David Fried, corporate vice president at Lam Rese... » read more

Using AI For Fault Detection And Classification In Manufacturing
By Ed Sperling - 05 Sep, 2025 - Comments: 0

Third in a seven-part series: Classic fault detection and classification has some classic problems. It's reactive, time-consuming to set up, and any product change involves significant man-hours. Even then, it still misses a lot of problems, which result in scrap. This is where machine learning can excel, because it can sift through huge amounts of data from thousands of sensors and find outlie... » read more

Advanced Part Average Testing For Chips
By Ed Sperling - 26 Aug, 2025 - Comments: 0

Part average testing, one of the mainstays of semiconductor test, is becoming much more challenging at advanced nodes and in multi-die assemblies. In the past, PAT produced a Gaussian distribution that made it relatively simple to find outliers. That's no longer the case. Advanced packaging and leading-edge designs have unique attributes that determine which rules apply, such as the thickness o... » read more

How Semiconductor Fabs Use Water
By Gregory Haley - 25 Aug, 2025 - Comments: 0

Water — lots of it — is a critical enabler for advanced chip architectures, lithography, and back-end packaging. It feeds the ultra-pure water loops that touch every wafer, sluicing heat out of tools that run hotter at each node, and carrying spent chemistries to treatment. The natural reaction to reports that fabs “use millions of gallons of water” is concern, but the engineering re... » read more

Machine Learning In Semiconductor Manufacturing
By Ed Sperling - 22 Aug, 2025 - Comments: 0

Second in a seven-part series: Machine learning is a mathematical construct that is the foundation for nearly all the advancements in AI. ML came first, but it remains relevant even today. It can be applied to semiconductor fab for such things as predictive maintenance of manufacturing equipment, rather than just maintenance on a schedule, which decreases downtime. But getting this right is har... » read more

Why 3D NAND Layers Bend (And How To Prevent It)
By Brett Lowe - 21 Aug, 2025 - Comments: 0

3D NAND flash memory is built by vertically stacking multiple alternating layers (tiers) of silicon nitride (SiN) and oxide (TEOS) on top of each other. A major challenge in producing multilayered 3D NAND devices is tier bending and tier collapse. These undesirable conditions can be caused by a combination of factors. Using the virtual Design of Experiment (DOE) capabilities in SEMulator... » read more

Materials Modeling Of Superconducting Qubits In Quantum Computers
By Anders Blom - 21 Aug, 2025 - Comments: 0

While the concept of quantum computing has been discussed for more than 40 years, only recently have experiments indicated that a practical quantum computer may be possible. Recent developments in this area have captured headlines with dramatic claims—and equally dramatic rebuttals. Google’s Willow chip demonstrated error-corrected operations in late 2024, while D-Wave’s assertion of quan... » read more

Manufacturing At The Limits
By Gregory Haley - 21 Aug, 2025 - Comments: 2

Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

How Guardbanding Of Inline Wafer Defects Can Improve Chip Reliability Insurance
By Errol Akomer - 21 Aug, 2025 - Comments: 0

Partially defective, marginal die can still be functional enough to pass final electrical test. Some of these “walking wounded” chips get past final testing, but in the customer's end product, under ongoing stress, they may fail. This is a particularly serious issue with automotive, medical and other customers who demand maximum long-term device reliability. The semiconductor industry ha... » read more

Reticle Stitching Bumps Up Silicon Interposer Costs
By Bryon Moyer - 21 Aug, 2025 - Comments: 0

Advanced packaging often relies on silicon interposers to connect chiplets and other components inside a package. The problem is that interposers typically exceed the reticle limit, which adds both complexity and cost. An interposer is essential for 2.5D and 3.5D architectures. As device scaling runs out of steam, chipmakers are decomposing planar SoCs into chiplets and connecting them throu... » read more

← Older posts Newer posts →

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy