Piecing Together Chiplets

By Mark LaPedus - 22 Jul, 2021 - Comments: 3

Several companies are implementing the chiplet model as a means to develop next-generation 3D-like chip designs, but this methodology still has a long way to go before it becomes mainstream for the rest of the industry. It takes several pieces to bring up a 3D chip design using the chiplet model. A few large players have the pieces, though most are proprietary. Others are missing some key co... » read more

Underlayer Optimization Method For EUV Lithography

By Brewer Science - 21 Jul, 2021 - Comments: 0

Photoresist and underlayer combine to serve a central role in EUVL for patterning. Layers will be very thin in future, because high numerical aperture (NA) and tight pitches will require very thin layers in the lithography stack. This thinness will make chemical interactions at the photoresist-underlayer interface more common. Adhesion between these layers will be critical to overcome pattern c... » read more

Survey: 2020 eBeam Initiative Annual Survey Results

By eBeam Initiative - 21 Jul, 2021 - Comments: 0

Aki Fujimura, the CEO of D2S, Inc. presented "The eBeam Initiative's Annual Survey Results at Photomask" at Photomask Japan 2021 in April 2021. Survey says that COVID has a net neutral business impact on total mask revenues. By 2021, 24% positive vs 20% negative COVID-related business predictions. 74% agree actinic inspection for EUV HVM by 2023, and more results. Click here to read more. » read more

Will An Adhesion Promoter Prevent Delamination In Power Semiconductor Packages?

By Amkor - 21 Jul, 2021 - Comments: 0

Power semiconductor packages are used in high temperature, high voltage environments. With the increase of electric vehicles (EVs) and hybrid electric vehicles (HEV) in the automotive market, demands on (and for) power packages have been growing. Packages for automotive applications must pass extensive testing for safety, therefore, packaging reliability is essential. As more semiconductor pack... » read more

Innovative Dual Mark Design For Alignment Verification And Process Monitoring In Advanced Lithography

By UMC - 21 Jul, 2021 - Comments: 0

Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. . . . With smart placement of alignment mark pairs in the X and Y direction, it is possible to determine intra-wafer distortion wafer-by-wafer. Both the measurement and modeled results are applied directly as a feed-forward correction to enable wafer level control. In this p... » read more

The Effects Of Poly Corner Etch Residue On Advanced FinFET Device Performance

By Coventor - 21 Jul, 2021 - Comments: 0

In this paper, we study the effect of poly corner residue during a 5nm FinFET poly etch process using virtual fabrication. A systemic investigation was performed to understand the impact of poly corner residue on hard failure modes and device performance. Our results indicate that larger width and height residues can lead to a hard failure by creating a short between the source/drain epitaxy an... » read more

Manufacturing Bits: July 20

By Mark LaPedus - 20 Jul, 2021 - Comments: 0

Interference EUV lithography ESOL has developed a standalone interference extreme ultraviolet (EUV) lithography tool for use in R&D applications. The system, called EMiLE (EUV Micro-interference Lithography Equipment), is primary used to speed up the development of EUV photoresists and related wafer processes. The system is different than ASML’s EUV lithography scanners, which are ... » read more

Behind The Intel-GlobalFoundries Rumor

By Ed Sperling - 19 Jul, 2021 - Comments: 5

A Wall Street Journal report that Intel is looking to buy GlobalFoundries has sparked discussions across the industry. But what exactly this would mean, and why now versus a couple years ago, needs some context. There are layers upon layers of irony behind this would-be deal, and it dates back decades to some rather famous encounters. Consider former AMD CEO Jerry Sanders' 1991 comment that ... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 16 Jul, 2021 - Comments: 0

Chipmakers The chip industry is buzzing over a Wall Street Journal report that Intel is in talks to buy GlobalFoundries (GF) for $30 billion. In March, Intel re-entered the foundry business, positioning itself against Samsung and TSMC at the leading edge, and against a multitude of foundries working at older nodes. Intel planned to jumpstart its foundry business within its own fabs. But it... » read more

Manufacturing Bits: July 13

By Mark LaPedus - 13 Jul, 2021 - Comments: 0

Heterogenous III-V packaging At the recent 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), a group presented a paper on the development of a wafer-level fan-out package using heterogenous III-V devices. This paper deals with the packaging of two III-V chips for use in RF transceiver applications in base stations. III-V Lab, CEA-Leti, Thales and United Monolithic Semic... » read more

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