AI Chips: NoC Interconnect IP Solves Three Design Challenges


New network-on-chip (NoC) interconnect IP is now available for artificial intelligence (AI) systems-on-chip (SoC). Arteris IP launched the fourth generation of the FlexNoC interconnect IP with a new optional AI package. The novel NoC interconnect technologies solves many data flow problems in today’s AI designs. Innovative features address the requirements of the next-generation of AI chips t... » read more

Edge Inferencing Challenges


Geoff Tate, CEO of Flex Logix, talks about balancing different variables to improve performance and reduce power at the lowest cost possible in order to do inferencing in edge devices. https://youtu.be/1BTxwew--5U » read more

Architecting a Hardware-Managed Hybrid DIMM Optimized for Cost/Performance


Authors: Fred Ware,(1) Javier Bueno,(2) Liji Gopalakrishnan,(1) Brent Haukness,(1) Chris Haywood,(1) Toni Juan,(2) Eric Linstadt,(1) Sally A. McKee,(3) Steven C. Woo,(1) Kenneth L. Wright,(1) Craig Hampel,(1) Gary Bronner.(1) (1) Rambus Inc. Sunnyvale, California (2) Metempsy, Barcelona, Spain (3) Clemson University, South Carolina Rapidly evolving workloads and exploding data volumes ... » read more

Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product


Written by Kurt Shuler, VP of Marketing at Arteris IP Developers of automotive semiconductor devices and electronic systems beware: There may be some vendors who claim their products meet the ISO 26262 safety standard requirements for integration into the production of passenger vehicles without fully understanding the nature of the challenge. These claims might be superficial if they fail... » read more

Generative Design for Autonomous Vehicle Electrical Systems


The massive complexity inherent in autonomous vehicle design will push the tools and methodologies used by automotive engineers to their limits. This is especially true in the electrical and electronic systems domains as they come to dominate the operation of a vehicle’s safety-critical systems and amenities. To compete, autonomous car manufacturers will need a new design methodology that ena... » read more

Overview of NMAX Neural Inferencing


At HotChips 2018, Microsoft presented the attached slide in their Brainwave presentation: the ideal is to achieve high hardware utilization at low batch size. Existing architectures don’t do this: they have high utilization only at high batch sizes which means high latency. NMAX’ architecture loads weights quickly achieving almost the same high utilization at batch=1 as at large batch sizes... » read more

Speedchip FPGA Chiplets


Next-generation SoC platforms are evolving rapidly to process and move enormous amounts of data from the edge; over the network and to the cloud for high data and compute intensive applications such as AI and machine learning, high-performance computing (HPC) and autonomous driving. As a result, next-generation ASICs need to be larger, faster and further optimized for performance, power and are... » read more

Get Smart with NB-IoT


NB-IoT is an emerging technology for narrowband wireless communication standardized by 3GPP. It has been designed with a focus on minimizing end-user equipment processing requirements and power consumption to enable the massive deployment of low-cost devices for a broad range of smart applications. This white paper highlights the key challenges of NB-IoT modem design. It proposes a hardware/so... » read more

Mixed-Signal Methodology Guide


ClioSoft wrote the chapter on SoC design data management in Cadence’s "Mixed-Signal Methodology Guide." Register to receive an electronic copy of this chapter. Introduction Software teams have long used version control and data management systems and they have become an integral part of a software development environment. Practically, no significant software project is started without a so... » read more

Consolidating RF Flow for High-Frequency Product Design


Design flows are currently fragmented due to the use of poorly connected EDA tools for various design tasks. Fragmented flows are unable to meet new challenges such as increased system and circuit complexity, stricter bandwidth requirements, smaller device sizes, and changing packaging needs. In this white paper, we look at how the Cadence Virtuoso RF Solution provides a single, well-integrated... » read more

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